[PATCH 02/12] dt-bindings: riscv: sifive-ccache: Add 'uncached-offset' property

Cristian Ciocaltea
2023-02-11T03:19:01Z

Add the 'uncached-offset' property to be used for specifying the
uncached memory offset required for handling non-coherent DMA
transactions.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml | 5 +++++
1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
index 2b864b2f12c9..60cd87a2810a 100644
--- a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
+++ b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
@@ -82,6 +82,11 @@ properties:

next-level-cache: true

+ uncached-offset:
+ $ref: /schemas/types.yaml#/definitions/uint64
+ description: |
+ Uncached memory offset for handling non-coherent DMA transactions.
+
memory-region:
maxItems: 1
description: |
--
2.39.1