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[47.55.122.23]) by smtp.gmail.com with ESMTPSA id i8-20020a05620a404800b006bc192d277csm16352660qko.10.2022.10.12.07.38.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Oct 2022 07:38:31 -0700 (PDT) Received: from jgg by wakko with local (Exim 4.95) (envelope-from ) id 1oicsP-001y84-7s; Wed, 12 Oct 2022 11:38:29 -0300 Date: Wed, 12 Oct 2022 11:38:29 -0300 From: Jason Gunthorpe To: "Radovanovic, Aleksandar" Cc: "Gupta, Nipun" , Marc Zyngier , Robin Murphy , "robh+dt@kernel.org" , "krzysztof.kozlowski+dt@linaro.org" , "gregkh@linuxfoundation.org" , "rafael@kernel.org" , "eric.auger@redhat.com" , "alex.williamson@redhat.com" , "cohuck@redhat.com" , "Gupta, Puneet (DCG-ENG)" , "song.bao.hua@hisilicon.com" , "mchehab+huawei@kernel.org" , "f.fainelli@gmail.com" , "jeffrey.l.hugo@gmail.com" , "saravanak@google.com" , "Michael.Srba@seznam.cz" , "mani@kernel.org" , "yishaih@nvidia.com" , "will@kernel.org" , "joro@8bytes.org" , "masahiroy@kernel.org" , "ndesaulniers@google.com" , "linux-arm-kernel@lists.infradead.org" , "linux-kbuild@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" , "kvm@vger.kernel.org" , "okaya@kernel.org" , "Anand, Harpreet" , "Agarwal, Nikhil" , "Simek, Michal" , "git (AMD-Xilinx)" Subject: Re: [RFC PATCH v3 4/7] bus/cdx: add cdx-MSI domain with gic-its domain as parent Message-ID: References: <20220803122655.100254-1-nipun.gupta@amd.com> <20220906134801.4079497-1-nipun.gupta@amd.com> <20220906134801.4079497-5-nipun.gupta@amd.com> <87h71juxuk.wl-maz@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Wed, Oct 12, 2022 at 01:37:54PM +0000, Radovanovic, Aleksandar wrote: > > On Wed, Oct 12, 2022 at 10:34:23AM +0000, Radovanovic, Aleksandar wrote: > > > > > > > As for GITS_TRANSLATER, we can take up to 4 different IOVAs, which > > > limits us to 4 CDX devices (should be sufficient for current HW > > > use-cases). Also, it means that the address part must be the same for > > > all vectors within a single CDX device. I'm assuming this is OK as it > > > is going to be a single interrupt and IOMMU domain anyway. > > > > This is not at all how MSI is supposed to work. > > In the general case, no, they're not. I don't mean that you can hack this to work - I mean that in MSI the addr/data is supposed to come from the end point itself, not from some kind of shared structure. This is important because the actual act of generating the write has to be coherent with the DMA the device is doing, as the MSI write must push any DMA data to visibility to meet the "producer / consumer" model. So it is really weird/wrong to have a HW design where the MSI infrastructure is shared across many devices. Jason