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Date:   Sun, 30 Oct 2022 22:39:44 +0000
From:   Conor Dooley <conor@kernel.org>
To:     "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Cc:     Guo Ren <guoren@kernel.org>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Geert Uytterhoeven <geert+renesas@glider.be>,
        Magnus Damm <magnus.damm@gmail.com>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Heiko Stuebner <heiko@sntech.de>,
        Conor Dooley <conor.dooley@microchip.com>,
        Anup Patel <anup@brainfault.org>,
        Atish Patra <atishp@rivosinc.com>,
        Heinrich Schuchardt <heinrich.schuchardt@canonical.com>,
        devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
        linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
        Biju Das <biju.das.jz@bp.renesas.com>,
        Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH v5 4/7] riscv: dts: renesas: Add initial devicetree for
 Renesas RZ/Five SoC
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On Sun, Oct 30, 2022 at 10:27:17PM +0000, Lad, Prabhakar wrote:
> Hi Conor,

> > > You could just move the below part to the second dtsi patch. Then
> > > compile won't be broken.
> > >
> > >             clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
> > >             power-domains = <&cpg>;
> > >             resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
> >
> > The makefile for this directory is not added until the next patch right?
> > The compile shouldn't be broken here since it therefore cannot be
> > compiled?
> >
> These nodes are already present in the kernel [0]  so the makefile
> change in the next patch if made here still won't break the
> compilation alone of SoC DTSI (included in dts).

Yeah I know, I did actually build the dtb ;)
I was just confused as to how Guo Ren had found a build issue with this
patch that the follow on patch would fix, when this dtsi is not
buildable in this patch.