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[98.239.145.235]) by smtp.gmail.com with ESMTPSA id f20-20020a02a114000000b00363961f0f2dsm2140039jag.115.2022.10.19.07.32.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Oct 2022 07:32:43 -0700 (PDT) Date: Wed, 19 Oct 2022 10:32:41 -0400 From: Brian Masney To: Johan Hovold Cc: Stanimir Varbanov , Lorenzo Pieralisi , Andy Gross , Bjorn Andersson , Konrad Dybcio , Bjorn Helgaas , Rob Herring , Krzysztof Kozlowski , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Krishna chaitanya chundru , quic_vbadigan@quicinc.com, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/2] PCI: qcom: Add basic interconnect support Message-ID: References: <20221017112449.2146-1-johan+linaro@kernel.org> <20221017112449.2146-3-johan+linaro@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20221017112449.2146-3-johan+linaro@kernel.org> User-Agent: Mutt/2.2.7 (2022-08-07) Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Mon, Oct 17, 2022 at 01:24:49PM +0200, Johan Hovold wrote: > + /* > + * Some Qualcomm platforms require interconnect bandwidth constraints > + * to be set before enabling interconnect clocks. > + * > + * Set an initial peak bandwidth corresponding to single-lane Gen 1 > + * for the pcie-mem path. > + */ > + ret = icc_set_bw(pcie->icc_mem, 0, MBps_to_icc(250)); [snip] > + speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, status); > + width = FIELD_GET(PCI_EXP_LNKSTA_NLW, status); > + > + switch (speed) { > + case 1: > + bw = MBps_to_icc(250); > + break; > + case 2: > + bw = MBps_to_icc(500); > + break; > + default: > + case 3: > + bw = MBps_to_icc(985); > + break; > + } Just curious: These platforms have a 4 lane PCIe bus. Why use 985 instead of 1000 for the maximum? Brian