From: Jisheng Zhang <jszhang@kernel.org>
To: Pierre Gondois <pierre.gondois@arm.com>
Cc: linux-kernel@vger.kernel.org, Rob.Herring@arm.com,
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org
Subject: Re: [PATCH 19/20] arm64: dts: Update cache properties for synaptics
Date: Mon, 7 Nov 2022 23:18:40 +0800 [thread overview]
Message-ID: <Y2kh0C4YCvjOlI7g@xhacker> (raw)
In-Reply-To: <20221031092115.533560-1-pierre.gondois@arm.com>
On Mon, Oct 31, 2022 at 10:21:14AM +0100, Pierre Gondois wrote:
> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
>
> The recently added init_of_cache_level() function checks
> these properties. Add them if missing.
>
> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Jisheng Zhang <jszhang@kernel.org>
> ---
> arch/arm64/boot/dts/synaptics/berlin4ct.dtsi | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi b/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi
> index 0949acee4728..926da7e1a6ba 100644
> --- a/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi
> +++ b/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi
> @@ -64,6 +64,7 @@ cpu3: cpu@3 {
>
> l2: cache {
> compatible = "cache";
> + cache-level = <2>;
> };
>
> idle-states {
> --
> 2.25.1
>
prev parent reply other threads:[~2022-11-07 15:28 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-31 9:21 [PATCH 19/20] arm64: dts: Update cache properties for synaptics Pierre Gondois
2022-11-07 15:18 ` Jisheng Zhang [this message]
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