From: Vinod Koul <vkoul@kernel.org>
To: Abel Vesa <abel.vesa@linaro.org>
Cc: Andy Gross <agross@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konrad.dybcio@linaro.org>,
Kishon Vijay Abraham I <kishon@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org,
linux-phy@lists.infradead.org
Subject: Re: [PATCH 03/10] phy: qcom-qmp-ufs: Add SM8550 support
Date: Thu, 24 Nov 2022 23:25:44 +0530 [thread overview]
Message-ID: <Y3+wIOQqH0uWx4TU@matsya> (raw)
In-Reply-To: <20221116120157.2706810-4-abel.vesa@linaro.org>
On 16-11-22, 14:01, Abel Vesa wrote:
> Add SM8550 specific register layout and table configs.
>
> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 91 +++++++++++++++++++++++++
> 1 file changed, 91 insertions(+)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> index 189103d1bd18..14cb716752e6 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> @@ -96,6 +96,13 @@ static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
> [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL,
> };
>
> +static const unsigned int sm8550_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_START_CTRL] = QPHY_V6_PCS_UFS_PHY_START,
> + [QPHY_PCS_READY_STATUS] = QPHY_V6_PCS_UFS_READY_STATUS,
> + [QPHY_SW_RESET] = QPHY_V6_PCS_UFS_SW_RESET,
> + [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_UFS_POWER_DOWN_CONTROL,
> +};
> +
> static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
> QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
> QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
> @@ -520,6 +527,65 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = {
> QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
> };
>
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
> +};
Unused?
> +
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
> +
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xc2),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6, 0x60),
> +
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B3, 0x9e),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B6, 0x60),
> +
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B3, 0x9e),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B4, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B5, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = {
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x69),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
> +};
> +
> struct qmp_ufs_offsets {
> u16 serdes;
> u16 pcs;
> @@ -613,6 +679,10 @@ static const char * const sm8450_ufs_phy_clk_l[] = {
> "qref", "ref", "ref_aux",
> };
>
> +static const char * const sm8550_ufs_phy_clk_l[] = {
> + "qref", "ref",
> +};
> +
> static const char * const sdm845_ufs_phy_clk_l[] = {
> "ref", "ref_aux",
> };
> @@ -766,6 +836,24 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
> .regs = sm8150_ufsphy_regs_layout,
> };
>
> +static const struct qmp_phy_cfg sm8550_ufsphy_cfg = {
> + .lanes = 2,
> +
> + .serdes_tbl = sm8550_ufsphy_serdes,
> + .serdes_tbl_num = ARRAY_SIZE(sm8550_ufsphy_serdes),
> + .tx_tbl = sm8550_ufsphy_tx,
> + .tx_tbl_num = ARRAY_SIZE(sm8550_ufsphy_tx),
> + .rx_tbl = sm8550_ufsphy_rx,
> + .rx_tbl_num = ARRAY_SIZE(sm8550_ufsphy_rx),
> + .pcs_tbl = sm8550_ufsphy_pcs,
> + .pcs_tbl_num = ARRAY_SIZE(sm8550_ufsphy_pcs),
> + .clk_list = sm8550_ufs_phy_clk_l,
> + .num_clks = ARRAY_SIZE(sm8550_ufs_phy_clk_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8550_ufsphy_regs_layout,
> +};
> +
> static void qmp_ufs_configure_lane(void __iomem *base,
> const struct qmp_phy_init_tbl tbl[],
> int num,
> @@ -1189,6 +1277,9 @@ static const struct of_device_id qmp_ufs_of_match_table[] = {
> }, {
> .compatible = "qcom,sm8450-qmp-ufs-phy",
> .data = &sm8450_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,sm8550-qmp-ufs-phy",
> + .data = &sm8550_ufsphy_cfg,
> },
> { },
> };
> --
> 2.34.1
--
~Vinod
next prev parent reply other threads:[~2022-11-24 17:56 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-16 12:01 [PATCH 00/10] phy: qualcomm: Add support for SM8550 Abel Vesa
2022-11-16 12:01 ` [PATCH 01/10] phy: qcom-qmp: qserdes-com: Add v6 register offsets Abel Vesa
2022-11-24 17:54 ` Vinod Koul
2022-11-16 12:01 ` [PATCH 02/10] dt-bindings: phy: Add QMP UFS PHY comptible for SM8550 Abel Vesa
2022-11-16 13:46 ` Johan Hovold
2022-11-16 12:01 ` [PATCH 03/10] phy: qcom-qmp-ufs: Add SM8550 support Abel Vesa
2022-11-17 15:36 ` kernel test robot
2022-11-24 17:55 ` Vinod Koul [this message]
2022-11-16 12:01 ` [PATCH 04/10] dt-bindings: phy: qcom,qmp-usb: Document SM8550 compatible Abel Vesa
2022-11-16 13:46 ` Johan Hovold
2023-01-23 10:19 ` Johan Hovold
2023-01-23 10:48 ` Abel Vesa
2023-01-23 10:49 ` Johan Hovold
2022-11-16 12:01 ` [PATCH 05/10] phy: qualcomm: qmp-usb: Add support for SM8550 Abel Vesa
2022-11-17 16:17 ` kernel test robot
2022-11-24 17:56 ` Vinod Koul
2022-11-16 12:01 ` [PATCH 06/10] dt-bindings: phy: qcom,qmp-pcie: Document SM8550 compatible Abel Vesa
2022-11-16 13:47 ` Johan Hovold
2022-11-16 12:01 ` [PATCH 07/10] phy: qualcomm: qmp-pcie: Add support for SM8550 g3x2 and g4x2 PCIEs Abel Vesa
2023-01-01 20:15 ` Dmitry Baryshkov
2023-01-17 13:57 ` Abel Vesa
2023-01-17 14:08 ` Dmitry Baryshkov
2022-11-16 12:01 ` [PATCH 08/10] dt-bindings: phy: Add qcom,snps-eusb2-phy schema file Abel Vesa
2022-11-16 15:29 ` Rob Herring
2022-11-16 15:44 ` Rob Herring
2022-11-16 12:01 ` [PATCH 09/10] phy: qualcomm: Add QCOM SNPS eUSB2 driver Abel Vesa
2022-11-24 18:01 ` Vinod Koul
2022-11-16 12:01 ` [PATCH 10/10] phy: qualcomm: phy-qcom-snps-eusb2: Add support for eUSB2 repeater Abel Vesa
2022-11-17 1:43 ` kernel test robot
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