* [PATCH 0/2] arm64: dts: qcom: sm8550: Add UFS HC and PHY
@ 2022-11-16 12:51 Abel Vesa
2022-11-16 12:51 ` [PATCH 1/2] arm64: dts: qcom: sm8550: Add UFS host controller and phy nodes Abel Vesa
2022-11-16 12:51 ` [PATCH 2/2] arm64: dts: qcom: sm8550-mtp: Add UFS host controller and PHY node Abel Vesa
0 siblings, 2 replies; 7+ messages in thread
From: Abel Vesa @ 2022-11-16 12:51 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski
Cc: Linux Kernel Mailing List, devicetree, linux-arm-msm
This patchset adds UFS HC and PHY support to SM8550 platform and to its
MTP board.
This patchset depends following patchsets:
[1] https://lore.kernel.org/all/20221116103146.2556846-1-abel.vesa@linaro.org/
[2] https://lore.kernel.org/all/20221116114526.2679041-1-abel.vesa@linaro.org/
Abel Vesa (2):
arm64: dts: qcom: sm8550: Add UFS host controller and phy nodes
arm64: dts: qcom: sm8550-mtp: Add UFS host controller and PHY node
arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 22 +++++++
arch/arm64/boot/dts/qcom/sm8550.dtsi | 76 +++++++++++++++++++++++++
2 files changed, 98 insertions(+)
--
2.34.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 1/2] arm64: dts: qcom: sm8550: Add UFS host controller and phy nodes
2022-11-16 12:51 [PATCH 0/2] arm64: dts: qcom: sm8550: Add UFS HC and PHY Abel Vesa
@ 2022-11-16 12:51 ` Abel Vesa
2022-11-16 12:58 ` Konrad Dybcio
2022-11-16 13:31 ` Johan Hovold
2022-11-16 12:51 ` [PATCH 2/2] arm64: dts: qcom: sm8550-mtp: Add UFS host controller and PHY node Abel Vesa
1 sibling, 2 replies; 7+ messages in thread
From: Abel Vesa @ 2022-11-16 12:51 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski
Cc: Linux Kernel Mailing List, devicetree, linux-arm-msm
Add UFS host controller and PHY nodes.
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 76 ++++++++++++++++++++++++++++
1 file changed, 76 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 07ba709ca35f..27ce382cb594 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -1372,6 +1372,82 @@ mmss_noc: interconnect@1780000 {
qcom,bcm-voters = <&apps_bcm_voter>;
};
+ ufs_mem_phy: phy@1d80000 {
+ compatible = "qcom,sm8550-qmp-ufs-phy";
+ reg = <0x0 0x01d80000 0x0 0x200>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ clock-names = "ref", "qref";
+ clocks = <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
+ <&tcsr TCSR_UFS_CLKREF_EN>;
+
+ power-domains = <&gcc UFS_MEM_PHY_GDSC>;
+
+ resets = <&ufs_mem_hc 0>;
+ reset-names = "ufsphy";
+ status = "disabled";
+
+ ufs_mem_phy_lanes: phy@1d80400 {
+ reg = <0x0 0x01d81000 0x0 0x134>,
+ <0x0 0x01d81200 0x0 0x3d8>,
+ <0x0 0x01d80400 0x0 0x258>,
+ <0x0 0x01d81800 0x0 0x134>,
+ <0x0 0x01d81a00 0x0 0x3d8>;
+ #phy-cells = <0>;
+ };
+ };
+
+ ufs_mem_hc: ufshc@1d84000 {
+ compatible = "qcom,sm8550-ufshc", "qcom,ufshc",
+ "jedec,ufs-2.0";
+ reg = <0x0 0x01d84000 0x0 0x3000>;
+ interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&ufs_mem_phy_lanes>;
+ phy-names = "ufsphy";
+ lanes-per-direction = <2>;
+ #reset-cells = <1>;
+ resets = <&gcc GCC_UFS_PHY_BCR>;
+ reset-names = "rst";
+
+ power-domains = <&gcc UFS_PHY_GDSC>;
+
+ iommus = <&apps_smmu 0x60 0x0>;
+
+ interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
+
+ interconnect-names = "ufs-ddr", "cpu-ufs";
+ clock-names =
+ "core_clk",
+ "bus_aggr_clk",
+ "iface_clk",
+ "core_clk_unipro",
+ "ref_clk",
+ "tx_lane0_sync_clk",
+ "rx_lane0_sync_clk",
+ "rx_lane1_sync_clk";
+ clocks =
+ <&gcc GCC_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_UFS_PHY_AHB_CLK>,
+ <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+ <&rpmhcc RPMH_LN_BB_CLK3>,
+ <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
+ freq-table-hz =
+ <75000000 300000000>,
+ <0 0>,
+ <0 0>,
+ <75000000 300000000>,
+ <100000000 403000000>,
+ <0 0>,
+ <0 0>,
+ <0 0>;
+ status = "disabled";
+ };
+
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0x0 0x01f40000 0x0 0x20000>;
--
2.34.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/2] arm64: dts: qcom: sm8550-mtp: Add UFS host controller and PHY node
2022-11-16 12:51 [PATCH 0/2] arm64: dts: qcom: sm8550: Add UFS HC and PHY Abel Vesa
2022-11-16 12:51 ` [PATCH 1/2] arm64: dts: qcom: sm8550: Add UFS host controller and phy nodes Abel Vesa
@ 2022-11-16 12:51 ` Abel Vesa
2022-11-16 12:56 ` Konrad Dybcio
1 sibling, 1 reply; 7+ messages in thread
From: Abel Vesa @ 2022-11-16 12:51 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski
Cc: Linux Kernel Mailing List, devicetree, linux-arm-msm
Enable UFS host controller and PHY node on SM8550 MTP board.
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
index d4c8d5b2497e..fef7793a7dec 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
@@ -417,3 +417,25 @@ data-pins {
&uart7 {
status = "okay";
};
+
+&ufs_mem_hc {
+ status = "okay";
+
+ reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
+
+ vcc-supply = <&vreg_l17b_2p5>;
+ vcc-max-microamp = <1300000>;
+ vccq-supply = <&vreg_l1g_1p2>;
+ vccq-max-microamp = <1200000>;
+ vccq2-supply = <&vreg_l3g_1p2>;
+ vccq2-max-microamp = <100>;
+};
+
+&ufs_mem_phy {
+ status = "okay";
+
+ vdda-phy-supply = <&vreg_l1d_0p88>;
+ vdda-phy-max-microamp = <188000>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+ vdda-pll-max-microamp = <18300>;
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] arm64: dts: qcom: sm8550-mtp: Add UFS host controller and PHY node
2022-11-16 12:51 ` [PATCH 2/2] arm64: dts: qcom: sm8550-mtp: Add UFS host controller and PHY node Abel Vesa
@ 2022-11-16 12:56 ` Konrad Dybcio
2022-11-22 20:51 ` Abel Vesa
0 siblings, 1 reply; 7+ messages in thread
From: Konrad Dybcio @ 2022-11-16 12:56 UTC (permalink / raw)
To: Abel Vesa, Andy Gross, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski
Cc: Linux Kernel Mailing List, devicetree, linux-arm-msm
On 16/11/2022 13:51, Abel Vesa wrote:
> Enable UFS host controller and PHY node on SM8550 MTP board.
>
> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
> index d4c8d5b2497e..fef7793a7dec 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
> +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
> @@ -417,3 +417,25 @@ data-pins {
> &uart7 {
> status = "okay";
> };
> +
> +&ufs_mem_hc {
> + status = "okay";
Status last, please.
> +
> + reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
> +
> + vcc-supply = <&vreg_l17b_2p5>;
> + vcc-max-microamp = <1300000>;
All these -microamp properties are downstream and do not exist in the
mainline kernel. Remove them.
Konrad
> + vccq-supply = <&vreg_l1g_1p2>;
> + vccq-max-microamp = <1200000>;
> + vccq2-supply = <&vreg_l3g_1p2>;
> + vccq2-max-microamp = <100>;
> +};
> +
> +&ufs_mem_phy {
> + status = "okay";
> +
> + vdda-phy-supply = <&vreg_l1d_0p88>;
> + vdda-phy-max-microamp = <188000>;
> + vdda-pll-supply = <&vreg_l3e_1p2>;
> + vdda-pll-max-microamp = <18300>;
> +};
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] arm64: dts: qcom: sm8550: Add UFS host controller and phy nodes
2022-11-16 12:51 ` [PATCH 1/2] arm64: dts: qcom: sm8550: Add UFS host controller and phy nodes Abel Vesa
@ 2022-11-16 12:58 ` Konrad Dybcio
2022-11-16 13:31 ` Johan Hovold
1 sibling, 0 replies; 7+ messages in thread
From: Konrad Dybcio @ 2022-11-16 12:58 UTC (permalink / raw)
To: Abel Vesa, Andy Gross, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski
Cc: Linux Kernel Mailing List, devicetree, linux-arm-msm
On 16/11/2022 13:51, Abel Vesa wrote:
> Add UFS host controller and PHY nodes.
>
> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/sm8550.dtsi | 76 ++++++++++++++++++++++++++++
> 1 file changed, 76 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> index 07ba709ca35f..27ce382cb594 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> @@ -1372,6 +1372,82 @@ mmss_noc: interconnect@1780000 {
> qcom,bcm-voters = <&apps_bcm_voter>;
> };
>
> + ufs_mem_phy: phy@1d80000 {
> + compatible = "qcom,sm8550-qmp-ufs-phy";
> + reg = <0x0 0x01d80000 0x0 0x200>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
These three can go at the bottom.
> + clock-names = "ref", "qref";
> + clocks = <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
> + <&tcsr TCSR_UFS_CLKREF_EN>;
> +
> + power-domains = <&gcc UFS_MEM_PHY_GDSC>;
> +
> + resets = <&ufs_mem_hc 0>;
> + reset-names = "ufsphy";
> + status = "disabled";
> +
> + ufs_mem_phy_lanes: phy@1d80400 {
> + reg = <0x0 0x01d81000 0x0 0x134>,
> + <0x0 0x01d81200 0x0 0x3d8>,
> + <0x0 0x01d80400 0x0 0x258>,
> + <0x0 0x01d81800 0x0 0x134>,
> + <0x0 0x01d81a00 0x0 0x3d8>;
> + #phy-cells = <0>;
> + };
> + };
> +
> + ufs_mem_hc: ufshc@1d84000 {
> + compatible = "qcom,sm8550-ufshc", "qcom,ufshc",
> + "jedec,ufs-2.0";
> + reg = <0x0 0x01d84000 0x0 0x3000>;
> + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
> + phys = <&ufs_mem_phy_lanes>;
> + phy-names = "ufsphy";
> + lanes-per-direction = <2>;
> + #reset-cells = <1>;
> + resets = <&gcc GCC_UFS_PHY_BCR>;
> + reset-names = "rst";
> +
> + power-domains = <&gcc UFS_PHY_GDSC>;
> +
> + iommus = <&apps_smmu 0x60 0x0>;
> +
> + interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
> +
> + interconnect-names = "ufs-ddr", "cpu-ufs";
> + clock-names =
Why break the line before adding any entries?
Konrad
> + "core_clk",
> + "bus_aggr_clk",
> + "iface_clk",
> + "core_clk_unipro",
> + "ref_clk",
> + "tx_lane0_sync_clk",
> + "rx_lane0_sync_clk",
> + "rx_lane1_sync_clk";
> + clocks =
> + <&gcc GCC_UFS_PHY_AXI_CLK>,
> + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
> + <&gcc GCC_UFS_PHY_AHB_CLK>,
> + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
> + <&rpmhcc RPMH_LN_BB_CLK3>,
> + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
> + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
> + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
> + freq-table-hz =
> + <75000000 300000000>,
> + <0 0>,
> + <0 0>,
> + <75000000 300000000>,
> + <100000000 403000000>,
> + <0 0>,
> + <0 0>,
> + <0 0>;
> + status = "disabled";
> + };
> +
> tcsr_mutex: hwlock@1f40000 {
> compatible = "qcom,tcsr-mutex";
> reg = <0x0 0x01f40000 0x0 0x20000>;
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] arm64: dts: qcom: sm8550: Add UFS host controller and phy nodes
2022-11-16 12:51 ` [PATCH 1/2] arm64: dts: qcom: sm8550: Add UFS host controller and phy nodes Abel Vesa
2022-11-16 12:58 ` Konrad Dybcio
@ 2022-11-16 13:31 ` Johan Hovold
1 sibling, 0 replies; 7+ messages in thread
From: Johan Hovold @ 2022-11-16 13:31 UTC (permalink / raw)
To: Abel Vesa
Cc: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Linux Kernel Mailing List, devicetree,
linux-arm-msm
On Wed, Nov 16, 2022 at 02:51:11PM +0200, Abel Vesa wrote:
> Add UFS host controller and PHY nodes.
>
> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/sm8550.dtsi | 76 ++++++++++++++++++++++++++++
> 1 file changed, 76 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> index 07ba709ca35f..27ce382cb594 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> @@ -1372,6 +1372,82 @@ mmss_noc: interconnect@1780000 {
> qcom,bcm-voters = <&apps_bcm_voter>;
> };
>
> + ufs_mem_phy: phy@1d80000 {
> + compatible = "qcom,sm8550-qmp-ufs-phy";
Where's the corresponding binding update?
> + reg = <0x0 0x01d80000 0x0 0x200>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + clock-names = "ref", "qref";
> + clocks = <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
> + <&tcsr TCSR_UFS_CLKREF_EN>;
> +
> + power-domains = <&gcc UFS_MEM_PHY_GDSC>;
> +
> + resets = <&ufs_mem_hc 0>;
> + reset-names = "ufsphy";
> + status = "disabled";
> +
> + ufs_mem_phy_lanes: phy@1d80400 {
> + reg = <0x0 0x01d81000 0x0 0x134>,
> + <0x0 0x01d81200 0x0 0x3d8>,
> + <0x0 0x01d80400 0x0 0x258>,
> + <0x0 0x01d81800 0x0 0x134>,
> + <0x0 0x01d81a00 0x0 0x3d8>;
> + #phy-cells = <0>;
> + };
This should be converted to use the new binding scheme which drops the
child node and individual register descriptions (cf. sc8280xp).
> + };
Johan
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] arm64: dts: qcom: sm8550-mtp: Add UFS host controller and PHY node
2022-11-16 12:56 ` Konrad Dybcio
@ 2022-11-22 20:51 ` Abel Vesa
0 siblings, 0 replies; 7+ messages in thread
From: Abel Vesa @ 2022-11-22 20:51 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Linux Kernel Mailing List, devicetree, linux-arm-msm
On 22-11-16 13:56:36, Konrad Dybcio wrote:
>
>
> On 16/11/2022 13:51, Abel Vesa wrote:
> > Enable UFS host controller and PHY node on SM8550 MTP board.
> >
> > Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> > ---
> > arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 22 ++++++++++++++++++++++
> > 1 file changed, 22 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
> > index d4c8d5b2497e..fef7793a7dec 100644
> > --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
> > +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
> > @@ -417,3 +417,25 @@ data-pins {
> > &uart7 {
> > status = "okay";
> > };
> > +
> > +&ufs_mem_hc {
> > + status = "okay";
> Status last, please.
Yep. Will do.
>
> > +
> > + reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
> > +
> > + vcc-supply = <&vreg_l17b_2p5>;
> > + vcc-max-microamp = <1300000>;
> All these -microamp properties are downstream and do not exist in the
> mainline kernel. Remove them.
>
Actually, ufshcd-qcom complains if they are missing:
[ 3.287836] ufshcd-qcom 1d84000.ufshc: ufshcd_populate_vreg: unable
to find vcc-max-microamp
[ 3.331904] ufshcd-qcom 1d84000.ufshc: ufshcd_populate_vreg: unable
to find vccq-max-microamp
[ 3.346766] ufshcd-qcom 1d84000.ufshc: ufshcd_populate_vreg: unable
to find vccq2-max-microamp
> Konrad
> > + vccq-supply = <&vreg_l1g_1p2>;
> > + vccq-max-microamp = <1200000>;
> > + vccq2-supply = <&vreg_l3g_1p2>;
> > + vccq2-max-microamp = <100>;
> > +};
> > +
> > +&ufs_mem_phy {
> > + status = "okay";
> > +
> > + vdda-phy-supply = <&vreg_l1d_0p88>;
> > + vdda-phy-max-microamp = <188000>;
These ones from PHY I can drop, since the driver won't complain.
> > + vdda-pll-supply = <&vreg_l3e_1p2>;
> > + vdda-pll-max-microamp = <18300>;
> > +};
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2022-11-22 20:51 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
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2022-11-16 12:51 [PATCH 0/2] arm64: dts: qcom: sm8550: Add UFS HC and PHY Abel Vesa
2022-11-16 12:51 ` [PATCH 1/2] arm64: dts: qcom: sm8550: Add UFS host controller and phy nodes Abel Vesa
2022-11-16 12:58 ` Konrad Dybcio
2022-11-16 13:31 ` Johan Hovold
2022-11-16 12:51 ` [PATCH 2/2] arm64: dts: qcom: sm8550-mtp: Add UFS host controller and PHY node Abel Vesa
2022-11-16 12:56 ` Konrad Dybcio
2022-11-22 20:51 ` Abel Vesa
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