[PATCH v2 00/10] ARM: dts: suniv: F1C100s: add more peripherals

[PATCH v2 00/10] ARM: dts: suniv: F1C100s: add more peripherals

[Andre Przywara]

This is a fixed version of the initial post. I dropped the two patches
that were already applied by the respective maintainers, and fixed the
smaller issues mentioned in the review.
This adds v2 of the series enabling the "Lctech Pi F1C200s" board on top,
also with the comments addressed.
The whole series goes on top of v3 of Icenowy's F1C100s USB support
series [1]. There is no real conflict, but the lctech-pi.dts file
references the new USB DT nodes from the .dtsi.

I put a git repo with all those patches up here:
https://github.com/apritzel/linux/commits/f1c100s-devices-v2

For a changelog see below.

[1] https://lore.kernel.org/linux-arm-kernel/20221106154826.6687-1-andre.przywara@arm.com/T/#t

=================
The Allwinner F1C100s series of SoCs shares many peripherals with other
Allwinner SoCs. Since they are compatible, we can use the existing
drivers, and just need to enable the devices in the DT.

This series adds the I2C controllers, the PWM device, the CIR (infrared)
device and the LRADC (aka. KEYADC, low res ADC) to the F1C100s .dtsi, so
boards can just use them by setting 'status = "okay";'.

The only thing missing driver-wise is the IR mod clock, which was not
modeled in our CCU driver. Patch 4/10 fixes that.

For every device there is one patch that adds the new compatible string
to the DT binding, and another patch to add the DT node.

This has been tested on the Lctech Pi F1C200s board, by:
- Connecting an LED to PE6, and configuring this as the PWM pin in the DT.
  Doing a sweep on /sys/class/pwm/pwm1/duty_cycle made the LED fade out.
- Configuring PD0/PD12 as I2C0, and letting i2c-detect find the on-board
  NS2009 I2C chip.
- Connecting two resistors to the "ADC" pin, and configuring them as two
  buttons in the DT. /dev/input/event0 properly reported button presses.
- Connecting an infrared receiver to PE11, configured as CIR.
  ir-keytable reported key presses on a remote control.

All those (basic) tests were successful, and prove that the peripherals
do work and are compatible.

The final three patches add the binding docs and the .dts file for the
Lctech Pi F1C200s development board.

Please have a look and test on your hardware, if possible.

Cheers,
Andre

Changelog v1 ... v2:
- dropped former patch 3/9 and 8/9: already applied
- increase register frame size in DT for PWM and LRADC
- drop I2C1 pins from pinctroller DT node
- increase IR mod clock mux to 2 bits
- fix mistyped comma in vendor prefix name
- drop unneeded mmc0 and spi0 aliases from Lctech Pi DT
- add /omit-if-no-ref/ tag to UART1 pins
- add ACKs and Reviewed-by tags


Andre Przywara (10):
  dt-bindings: pwm: allwinner,sun4i-a10: Add F1C100s compatible
  ARM: dts: suniv: f1c100s: add PWM node
  ARM: dts: suniv: f1c100s: add I2C DT nodes
  clk: sunxi-ng: f1c100s: Add IR mod clock
  dt-bindings: media: IR: Add F1C100s IR compatible string
  ARM: dts: suniv: f1c100s: add CIR DT node
  ARM: dts: suniv: f1c100s: add LRADC node
  dt-bindings: vendor-prefixes: add Lctech name
  dt-bindings: arm: sunxi: add compatible strings for Lctech Pi
  ARM: dts: suniv: Add Lctech Pi F1C200s devicetree

 .../devicetree/bindings/arm/sunxi.yaml        |  6 ++
 .../media/allwinner,sun4i-a10-ir.yaml         |  1 +
 .../bindings/pwm/allwinner,sun4i-a10-pwm.yaml |  4 +-
 .../devicetree/bindings/vendor-prefixes.yaml  |  2 +
 arch/arm/boot/dts/Makefile                    |  1 +
 arch/arm/boot/dts/suniv-f1c100s.dtsi          | 76 ++++++++++++++++++
 arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts | 78 +++++++++++++++++++
 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c      | 11 ++-
 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h      |  2 +-
 include/dt-bindings/clock/suniv-ccu-f1c100s.h |  2 +
 10 files changed, 180 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts

-- 
2.35.5

[PATCH v2 01/10] dt-bindings: pwm: allwinner,sun4i-a10: Add F1C100s compatible

[Andre Przywara]

The PWM controller in the Allwinner F1C100s series of SoCs is the same
as in the A20 SoCs, so allow using that as the fallback name.

Join the V3s compatible string in an enum on the way.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Rob Herring <robh@kernel.org>
---
 .../devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml      | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml b/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml
index 4cc3cc7c50be..66e400f2a3a4 100644
--- a/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml
+++ b/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml
@@ -25,7 +25,9 @@ properties:
           - const: allwinner,sun8i-a83t-pwm
           - const: allwinner,sun8i-h3-pwm
       - items:
-          - const: allwinner,sun8i-v3s-pwm
+          - enum:
+              - allwinner,suniv-f1c100s-pwm
+              - allwinner,sun8i-v3s-pwm
           - const: allwinner,sun7i-a20-pwm
       - items:
           - const: allwinner,sun50i-a64-pwm
-- 
2.35.5

Re: [PATCH v2 01/10] dt-bindings: pwm: allwinner,sun4i-a10: Add F1C100s compatible

[Uwe Kleine-König]

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On Mon, Nov 07, 2022 at 12:54:24AM +0000, Andre Przywara wrote:
> The PWM controller in the Allwinner F1C100s series of SoCs is the same
> as in the A20 SoCs, so allow using that as the fallback name.
> 
> Join the V3s compatible string in an enum on the way.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
>  .../devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml      | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml b/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml
> index 4cc3cc7c50be..66e400f2a3a4 100644
> --- a/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml
> +++ b/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml
> @@ -25,7 +25,9 @@ properties:
>            - const: allwinner,sun8i-a83t-pwm
>            - const: allwinner,sun8i-h3-pwm
>        - items:
> -          - const: allwinner,sun8i-v3s-pwm
> +          - enum:
> +              - allwinner,suniv-f1c100s-pwm
> +              - allwinner,sun8i-v3s-pwm

LGTM

Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-König            |
Industrial Linux Solutions                 | https://www.pengutronix.de/ |

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Re: [PATCH v2 01/10] dt-bindings: pwm: allwinner,sun4i-a10: Add F1C100s compatible

[Thierry Reding]

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On Mon, Nov 07, 2022 at 12:54:24AM +0000, Andre Przywara wrote:
> The PWM controller in the Allwinner F1C100s series of SoCs is the same
> as in the A20 SoCs, so allow using that as the fallback name.
> 
> Join the V3s compatible string in an enum on the way.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
>  .../devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml      | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)

Acked-by: Thierry Reding <thierry.reding@gmail.com>

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[PATCH v2 02/10] ARM: dts: suniv: f1c100s: add PWM node

[Andre Przywara]

The Allwinner F1C100s family of SoCs contain a PWM controller compatible
to the one used in the A20 chip.
Add the DT node so that any users can simply enable it in their board
DT.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 arch/arm/boot/dts/suniv-f1c100s.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
index a01541ba42c5..81749d5da12f 100644
--- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
+++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
@@ -218,6 +218,15 @@ wdt: watchdog@1c20ca0 {
 			clocks = <&osc32k>;
 		};
 
+		pwm: pwm@1c21000 {
+			compatible = "allwinner,suniv-f1c100s-pwm",
+				     "allwinner,sun7i-a20-pwm";
+			reg = <0x01c21000 0x400>;
+			clocks = <&osc24M>;
+			#pwm-cells = <3>;
+			status = "disabled";
+		};
+
 		uart0: serial@1c25000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x01c25000 0x400>;
-- 
2.35.5

Re: [PATCH v2 02/10] ARM: dts: suniv: f1c100s: add PWM node

[Jernej Škrabec]

Dne ponedeljek, 07. november 2022 ob 01:54:25 CET je Andre Przywara 
napisal(a):
> The Allwinner F1C100s family of SoCs contain a PWM controller compatible
> to the one used in the A20 chip.
> Add the DT node so that any users can simply enable it in their board
> DT.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>

Best regards,
Jernej

Re: [PATCH v2 02/10] ARM: dts: suniv: f1c100s: add PWM node

[Uwe Kleine-König]

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On Mon, Nov 07, 2022 at 12:54:25AM +0000, Andre Przywara wrote:
> The Allwinner F1C100s family of SoCs contain a PWM controller compatible
> to the one used in the A20 chip.
> Add the DT node so that any users can simply enable it in their board
> DT.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>

I checked "by hand" that this matches the modified binding in patch
01/10. 

Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>

I assume the whole series will go in via a tree different from the PWM
tree? While this is Thierry's area of maintenance, I'd be surprised if
he had concerns about that.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-König            |
Industrial Linux Solutions                 | https://www.pengutronix.de/ |

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Re: [PATCH v2 02/10] ARM: dts: suniv: f1c100s: add PWM node

[Thierry Reding]

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On Tue, Nov 15, 2022 at 11:19:26AM +0100, Uwe Kleine-König wrote:
> On Mon, Nov 07, 2022 at 12:54:25AM +0000, Andre Przywara wrote:
> > The Allwinner F1C100s family of SoCs contain a PWM controller compatible
> > to the one used in the A20 chip.
> > Add the DT node so that any users can simply enable it in their board
> > DT.
> > 
> > Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> 
> I checked "by hand" that this matches the modified binding in patch
> 01/10. 
> 
> Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
> 
> I assume the whole series will go in via a tree different from the PWM
> tree? While this is Thierry's area of maintenance, I'd be surprised if
> he had concerns about that.

Yeah, it's probably best for the Allwinner maintainers to pick this up
into their tree so that the bindings changes go along with the DT
changes.

Acked-by: Thierry Reding <thierry.reding@gmail.com>

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Re: [PATCH v2 02/10] ARM: dts: suniv: f1c100s: add PWM node

[Jernej Škrabec]

Dne torek, 15. november 2022 ob 11:25:12 CET je Thierry Reding napisal(a):
> On Tue, Nov 15, 2022 at 11:19:26AM +0100, Uwe Kleine-König wrote:
> > On Mon, Nov 07, 2022 at 12:54:25AM +0000, Andre Przywara wrote:
> > > The Allwinner F1C100s family of SoCs contain a PWM controller compatible
> > > to the one used in the A20 chip.
> > > Add the DT node so that any users can simply enable it in their board
> > > DT.
> > > 
> > > Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> > 
> > I checked "by hand" that this matches the modified binding in patch
> > 01/10.
> > 
> > Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
> > 
> > I assume the whole series will go in via a tree different from the PWM
> > tree? While this is Thierry's area of maintenance, I'd be surprised if
> > he had concerns about that.
> 
> Yeah, it's probably best for the Allwinner maintainers to pick this up
> into their tree so that the bindings changes go along with the DT
> changes.

Yeah, that's the plan. I'll merge it in following days.

Best regards,
Jernej

> 
> Acked-by: Thierry Reding <thierry.reding@gmail.com>

[PATCH v2 03/10] ARM: dts: suniv: f1c100s: add I2C DT nodes

[Andre Przywara]

The Allwinner F1C100s series of SoCs contain three I2C controllers
compatible to the ones used in other Allwinner SoCs.

Add the DT nodes describing the resources of the controllers.
I2C1 has only one possible pinmux, so add the pinctrl properties for
that already.
At least one board connects an on-board I2C chip to PD0/PD12 (I2C0), so
include those pins already, to simplify referencing them later.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 arch/arm/boot/dts/suniv-f1c100s.dtsi | 42 ++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
index 81749d5da12f..4f45168cea42 100644
--- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
+++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
@@ -192,6 +192,12 @@ mmc0_pins: mmc0-pins {
 				drive-strength = <30>;
 			};
 
+			/omit-if-no-ref/
+			i2c0_pd_pins: i2c0-pd-pins {
+				pins = "PD0", "PD12";
+				function = "i2c0";
+			};
+
 			spi0_pc_pins: spi0-pc-pins {
 				pins = "PC0", "PC1", "PC2", "PC3";
 				function = "spi0";
@@ -203,6 +209,42 @@ uart0_pe_pins: uart0-pe-pins {
 			};
 		};
 
+		i2c0: i2c@1c27000 {
+			compatible = "allwinner,suniv-f1c100s-i2c",
+				     "allwinner,sun6i-a31-i2c";
+			reg = <0x01c27000 0x400>;
+			interrupts = <7>;
+			clocks = <&ccu CLK_BUS_I2C0>;
+			resets = <&ccu RST_BUS_I2C0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c1: i2c@1c27400 {
+			compatible = "allwinner,suniv-f1c100s-i2c",
+				     "allwinner,sun6i-a31-i2c";
+			reg = <0x01c27400 0x400>;
+			interrupts = <8>;
+			clocks = <&ccu CLK_BUS_I2C1>;
+			resets = <&ccu RST_BUS_I2C1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c2: i2c@1c27800 {
+			compatible = "allwinner,suniv-f1c100s-i2c",
+				     "allwinner,sun6i-a31-i2c";
+			reg = <0x01c27800 0x400>;
+			interrupts = <9>;
+			clocks = <&ccu CLK_BUS_I2C2>;
+			resets = <&ccu RST_BUS_I2C2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		timer@1c20c00 {
 			compatible = "allwinner,suniv-f1c100s-timer";
 			reg = <0x01c20c00 0x90>;
-- 
2.35.5

Re: [PATCH v2 03/10] ARM: dts: suniv: f1c100s: add I2C DT nodes

[Jernej Škrabec]

Dne ponedeljek, 07. november 2022 ob 01:54:26 CET je Andre Przywara 
napisal(a):
> The Allwinner F1C100s series of SoCs contain three I2C controllers
> compatible to the ones used in other Allwinner SoCs.
> 
> Add the DT nodes describing the resources of the controllers.
> I2C1 has only one possible pinmux, so add the pinctrl properties for
> that already.

Above statement doesn't match current changes anymore. With that removed:
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>

If nothing else pops up, I can fix this while applying.

Best regards,
Jernej

> At least one board connects an on-board I2C chip to PD0/PD12 (I2C0), so
> include those pins already, to simplify referencing them later.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
>  arch/arm/boot/dts/suniv-f1c100s.dtsi | 42 ++++++++++++++++++++++++++++
>  1 file changed, 42 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi
> b/arch/arm/boot/dts/suniv-f1c100s.dtsi index 81749d5da12f..4f45168cea42
> 100644
> --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
> +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
> @@ -192,6 +192,12 @@ mmc0_pins: mmc0-pins {
>  				drive-strength = <30>;
>  			};
> 
> +			/omit-if-no-ref/
> +			i2c0_pd_pins: i2c0-pd-pins {
> +				pins = "PD0", "PD12";
> +				function = "i2c0";
> +			};
> +
>  			spi0_pc_pins: spi0-pc-pins {
>  				pins = "PC0", "PC1", "PC2", 
"PC3";
>  				function = "spi0";
> @@ -203,6 +209,42 @@ uart0_pe_pins: uart0-pe-pins {
>  			};
>  		};
> 
> +		i2c0: i2c@1c27000 {
> +			compatible = "allwinner,suniv-f1c100s-i2c",
> +				     "allwinner,sun6i-a31-i2c";
> +			reg = <0x01c27000 0x400>;
> +			interrupts = <7>;
> +			clocks = <&ccu CLK_BUS_I2C0>;
> +			resets = <&ccu RST_BUS_I2C0>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +
> +		i2c1: i2c@1c27400 {
> +			compatible = "allwinner,suniv-f1c100s-i2c",
> +				     "allwinner,sun6i-a31-i2c";
> +			reg = <0x01c27400 0x400>;
> +			interrupts = <8>;
> +			clocks = <&ccu CLK_BUS_I2C1>;
> +			resets = <&ccu RST_BUS_I2C1>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +
> +		i2c2: i2c@1c27800 {
> +			compatible = "allwinner,suniv-f1c100s-i2c",
> +				     "allwinner,sun6i-a31-i2c";
> +			reg = <0x01c27800 0x400>;
> +			interrupts = <9>;
> +			clocks = <&ccu CLK_BUS_I2C2>;
> +			resets = <&ccu RST_BUS_I2C2>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +
>  		timer@1c20c00 {
>  			compatible = "allwinner,suniv-f1c100s-
timer";
>  			reg = <0x01c20c00 0x90>;
> --
> 2.35.5

[PATCH v2 04/10] clk: sunxi-ng: f1c100s: Add IR mod clock

[Andre Przywara]

For some reason the mod clock for the Allwinner F1C100s CIR (infrared
receiver) peripheral was not modeled in the CCU driver.

Add the clock description to the list, and wire it up in the clock list.
By assigning a new clock ID at the end, it extends the number of clocks.

This allows to use the CIR peripheral on any F1C100s series board.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c      | 11 ++++++++++-
 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h      |  2 +-
 include/dt-bindings/clock/suniv-ccu-f1c100s.h |  2 ++
 3 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
index ed097c4f780f..0d5b60b123b7 100644
--- a/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
+++ b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
@@ -239,7 +239,14 @@ static SUNXI_CCU_MUX_WITH_GATE(i2s_clk, "i2s", i2s_spdif_parents,
 static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", i2s_spdif_parents,
 			       0x0b4, 16, 2, BIT(31), 0);
 
-/* The BSP header file has a CIR_CFG, but no mod clock uses this definition */
+static const char * const ir_parents[] = { "osc32k", "osc24M" };
+static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir",
+				  ir_parents, 0x0b8,
+				  0, 4,		/* M */
+				  16, 2,	/* P */
+				  24, 2,        /* mux */
+				  BIT(31),      /* gate */
+				  0);
 
 static SUNXI_CCU_GATE(usb_phy0_clk,	"usb-phy0",	"osc24M",
 		      0x0cc, BIT(1), 0);
@@ -355,6 +362,7 @@ static struct ccu_common *suniv_ccu_clks[] = {
 	&mmc1_output_clk.common,
 	&i2s_clk.common,
 	&spdif_clk.common,
+	&ir_clk.common,
 	&usb_phy0_clk.common,
 	&dram_ve_clk.common,
 	&dram_csi_clk.common,
@@ -446,6 +454,7 @@ static struct clk_hw_onecell_data suniv_hw_clks = {
 		[CLK_MMC1_OUTPUT]	= &mmc1_output_clk.common.hw,
 		[CLK_I2S]		= &i2s_clk.common.hw,
 		[CLK_SPDIF]		= &spdif_clk.common.hw,
+		[CLK_IR]		= &ir_clk.common.hw,
 		[CLK_USB_PHY0]		= &usb_phy0_clk.common.hw,
 		[CLK_DRAM_VE]		= &dram_ve_clk.common.hw,
 		[CLK_DRAM_CSI]		= &dram_csi_clk.common.hw,
diff --git a/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h
index b22484f1bb9a..d56a4316289d 100644
--- a/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h
+++ b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h
@@ -29,6 +29,6 @@
 
 /* All bus gates, DRAM gates and mod clocks are exported */
 
-#define CLK_NUMBER		(CLK_AVS + 1)
+#define CLK_NUMBER		(CLK_IR + 1)
 
 #endif /* _CCU_SUNIV_F1C100S_H_ */
diff --git a/include/dt-bindings/clock/suniv-ccu-f1c100s.h b/include/dt-bindings/clock/suniv-ccu-f1c100s.h
index f5ac155c9c70..d7570765f424 100644
--- a/include/dt-bindings/clock/suniv-ccu-f1c100s.h
+++ b/include/dt-bindings/clock/suniv-ccu-f1c100s.h
@@ -67,4 +67,6 @@
 #define CLK_CODEC		65
 #define CLK_AVS			66
 
+#define CLK_IR			67
+
 #endif
-- 
2.35.5

Re: [PATCH v2 04/10] clk: sunxi-ng: f1c100s: Add IR mod clock

[Jernej Škrabec]

Dne ponedeljek, 07. november 2022 ob 01:54:27 CET je Andre Przywara 
napisal(a):
> For some reason the mod clock for the Allwinner F1C100s CIR (infrared
> receiver) peripheral was not modeled in the CCU driver.
> 
> Add the clock description to the list, and wire it up in the clock list.
> By assigning a new clock ID at the end, it extends the number of clocks.
> 
> This allows to use the CIR peripheral on any F1C100s series board.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>

Best regards,
Jernej

[PATCH v2 05/10] dt-bindings: media: IR: Add F1C100s IR compatible string

[Andre Przywara]

The CIR controller in the Allwinner F1C100s series of SoCs is compatible
to the ones used in other Allwinner SoCs.

Add the respective compatible name to the existing IR binding, and pair
it with the A31 fallback compatible string.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Rob Herring <robh@kernel.org>
---
 .../devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml        | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml b/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml
index 704033e21ee8..53945c61325c 100644
--- a/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml
+++ b/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml
@@ -21,6 +21,7 @@ properties:
       - const: allwinner,sun6i-a31-ir
       - items:
           - enum:
+              - allwinner,suniv-f1c100s-ir
               - allwinner,sun8i-a83t-ir
               - allwinner,sun8i-r40-ir
               - allwinner,sun50i-a64-ir
-- 
2.35.5

[PATCH v2 06/10] ARM: dts: suniv: f1c100s: add CIR DT node

[Andre Przywara]

The CIR (infrared receiver) controller in the Allwinner F1C100s series
of SoCs is compatible to the ones used in other Allwinner SoCs.

Add the DT node describing the resources of the controller.
There are multiple possible pinmuxes, but none as them seem to be an
obvious choice, so refrain from adding any pincontroller subnodes for
now.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
---
 arch/arm/boot/dts/suniv-f1c100s.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
index 4f45168cea42..c04cd175f743 100644
--- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
+++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
@@ -269,6 +269,17 @@ pwm: pwm@1c21000 {
 			status = "disabled";
 		};
 
+		ir: ir@1c22c00 {
+			compatible = "allwinner,suniv-f1c100s-ir",
+				     "allwinner,sun6i-a31-ir";
+			reg = <0x01c22c00 0x400>;
+			clocks = <&ccu CLK_BUS_IR>, <&ccu CLK_IR>;
+			clock-names = "apb", "ir";
+			resets = <&ccu RST_BUS_IR>;
+			interrupts = <6>;
+			status = "disabled";
+		};
+
 		uart0: serial@1c25000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x01c25000 0x400>;
-- 
2.35.5

[PATCH v2 07/10] ARM: dts: suniv: f1c100s: add LRADC node

[Andre Przywara]

The Allwinner F1C100s series of SoCs contain a LRADC (aka. KEYADC)
compatible to the version in other SoCs.
The manual doesn't mention the ratio of the input voltage that is used,
but comparing actual measurements with the values in the register
suggests that it is 3/4 of Vref.

Add the DT node describing the base address and interrupt. As in the
older SoCs, there is no explicit reset or clock gate, also there is a
dedicated, non-multiplexed pin, so need for more properties.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
---
 arch/arm/boot/dts/suniv-f1c100s.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
index c04cd175f743..111f8bbc2a80 100644
--- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
+++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
@@ -280,6 +280,14 @@ ir: ir@1c22c00 {
 			status = "disabled";
 		};
 
+		lradc: lradc@1c23400 {
+			compatible = "allwinner,suniv-f1c100s-lradc",
+				     "allwinner,sun8i-a83t-r-lradc";
+			reg = <0x01c23400 0x400>;
+			interrupts = <22>;
+			status = "disabled";
+		};
+
 		uart0: serial@1c25000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x01c25000 0x400>;
-- 
2.35.5

[PATCH v2 08/10] dt-bindings: vendor-prefixes: add Lctech name

[Andre Przywara]

Shenzen LC Technology [1] is a company making various boards and related
products around IoT and AI technology.
They used to use the "Cherry Pi" brand before.

Add it to the vendor prefixes list.

[1] http://www.chinalctech.com

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 035ef859fbc5..65754cdc8bf8 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -695,6 +695,8 @@ patternProperties:
     description: Lantiq Semiconductor
   "^lattice,.*":
     description: Lattice Semiconductor
+  "^lctech,.*":
+    description: Shenzen LC Technology Co., Ltd.
   "^leadtek,.*":
     description: Shenzhen Leadtek Technology Co., Ltd.
   "^leez,.*":
-- 
2.35.5

Re: [PATCH v2 08/10] dt-bindings: vendor-prefixes: add Lctech name

[Jernej Škrabec]

Dne ponedeljek, 07. november 2022 ob 01:54:31 CET je Andre Przywara 
napisal(a):
> Shenzen LC Technology [1] is a company making various boards and related
> products around IoT and AI technology.
> They used to use the "Cherry Pi" brand before.
> 
> Add it to the vendor prefixes list.
> 
> [1] http://www.chinalctech.com
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>

Best regards,
Jernej

Re: [PATCH v2 08/10] dt-bindings: vendor-prefixes: add Lctech name

[Krzysztof Kozlowski]

On 07/11/2022 01:54, Andre Przywara wrote:
> Shenzen LC Technology [1] is a company making various boards and related
> products around IoT and AI technology.
> They used to use the "Cherry Pi" brand before.
> 
> Add it to the vendor prefixes list.
> 


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

[PATCH v2 09/10] dt-bindings: arm: sunxi: add compatible strings for Lctech Pi

[Andre Przywara]

The Lctech Pi F1C200s is a small development board using the Allwinner
F1C200s SoC.

Add the compatible string list to the bindings documentation.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 Documentation/devicetree/bindings/arm/sunxi.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml
index c6e0ad7f461d..cbdfc1c247a2 100644
--- a/Documentation/devicetree/bindings/arm/sunxi.yaml
+++ b/Documentation/devicetree/bindings/arm/sunxi.yaml
@@ -366,6 +366,12 @@ properties:
           - const: lamobo,lamobo-r1
           - const: allwinner,sun7i-a20
 
+      - description: Lctech Pi F1C200s
+        items:
+          - const: lctech,pi-f1c200s
+          - const: allwinner,suniv-f1c200s
+          - const: allwinner,suniv-f1c100s
+
       - description: Libre Computer Board ALL-H3-CC H2+
         items:
           - const: libretech,all-h3-cc-h2-plus
-- 
2.35.5

[PATCH v2 10/10] ARM: dts: suniv: Add Lctech Pi F1C200s devicetree

[Andre Przywara]

The Lctech Pi F1C200s (also previously known under the Cherry Pi brand)
is a small development board with the Allwinner F1C200s SoC. This is the
same as the F1C100s, but with 64MB instead of 32MB co-packaged DRAM.

Alongside the obligatory micro-SD card slot, the board features a
SPI-NAND flash chip, LCD and touch connectors, and unpopulated
expansion header pins.
There are two USB Type-C ports on the board: One supplies the power, also
connects to the USB MUSB OTG controller port. The other one is connected
to an CH340 USB serial chip, which in turn is connected to UART1.

Add a devicetree file, so that the board can be used easily.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 arch/arm/boot/dts/Makefile                    |  1 +
 arch/arm/boot/dts/suniv-f1c100s.dtsi          |  6 ++
 arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts | 78 +++++++++++++++++++
 3 files changed, 85 insertions(+)
 create mode 100644 arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 0249c07bd8a6..52f8ab0eacb2 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1392,6 +1392,7 @@ dtb-$(CONFIG_MACH_SUN9I) += \
 	sun9i-a80-cubieboard4.dtb
 dtb-$(CONFIG_MACH_SUNIV) += \
 	suniv-f1c100s-licheepi-nano.dtb \
+	suniv-f1c200s-lctech-pi.dtb \
 	suniv-f1c200s-popstick-v1.1.dtb
 dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \
 	tegra20-acer-a500-picasso.dtb \
diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
index 111f8bbc2a80..3c61d59ab5f8 100644
--- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
+++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
@@ -207,6 +207,12 @@ uart0_pe_pins: uart0-pe-pins {
 				pins = "PE0", "PE1";
 				function = "uart0";
 			};
+
+			/omit-if-no-ref/
+			uart1_pa_pins: uart1-pa-pins {
+				pins = "PA2", "PA3";
+				function = "uart1";
+			};
 		};
 
 		i2c0: i2c@1c27000 {
diff --git a/arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts b/arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts
new file mode 100644
index 000000000000..14c26f2c19f6
--- /dev/null
+++ b/arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Arm Ltd,
+ * based on work:
+ *   Copyright 2022 Icenowy Zheng <uwu@icenowy.me>
+ */
+
+/dts-v1/;
+#include "suniv-f1c100s.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "Lctech Pi F1C200s";
+	compatible = "lctech,pi-f1c200s", "allwinner,suniv-f1c200s",
+		     "allwinner,suniv-f1c100s";
+
+	aliases {
+		serial0 = &uart1;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	reg_vcc3v3: regulator-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+};
+
+&mmc0 {
+	broken-cd;
+	bus-width = <4>;
+	disable-wp;
+	vmmc-supply = <&reg_vcc3v3>;
+	status = "okay";
+};
+
+&otg_sram {
+	status = "okay";
+};
+
+&spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi0_pc_pins>;
+	status = "okay";
+
+	flash@0 {
+		compatible = "spi-nand";
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-max-frequency = <40000000>;
+	};
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1_pa_pins>;
+	status = "okay";
+};
+
+/*
+ * This is a Type-C socket, but CC1/2 are not connected, and VBUS is connected
+ * to Vin, which supplies the board. Host mode works (if the board is powered
+ * otherwise), but peripheral is probably the intention.
+ */
+&usb_otg {
+	dr_mode = "peripheral";
+	status = "okay";
+};
+
+&usbphy {
+	status = "okay";
+};
-- 
2.35.5

Re: [PATCH v2 10/10] ARM: dts: suniv: Add Lctech Pi F1C200s devicetree

[Jernej Škrabec]

Dne ponedeljek, 07. november 2022 ob 01:54:33 CET je Andre Przywara 
napisal(a):
> The Lctech Pi F1C200s (also previously known under the Cherry Pi brand)
> is a small development board with the Allwinner F1C200s SoC. This is the
> same as the F1C100s, but with 64MB instead of 32MB co-packaged DRAM.
> 
> Alongside the obligatory micro-SD card slot, the board features a
> SPI-NAND flash chip, LCD and touch connectors, and unpopulated
> expansion header pins.
> There are two USB Type-C ports on the board: One supplies the power, also
> connects to the USB MUSB OTG controller port. The other one is connected
> to an CH340 USB serial chip, which in turn is connected to UART1.
> 
> Add a devicetree file, so that the board can be used easily.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>

Best regards,
Jernej

Re: [PATCH v2 00/10] ARM: dts: suniv: F1C100s: add more peripherals

[Jernej Škrabec]

Dne ponedeljek, 07. november 2022 ob 01:54:23 CET je Andre Przywara 
napisal(a):
> This is a fixed version of the initial post. I dropped the two patches
> that were already applied by the respective maintainers, and fixed the
> smaller issues mentioned in the review.
> This adds v2 of the series enabling the "Lctech Pi F1C200s" board on top,
> also with the comments addressed.

Please don't combine series if not agreed upon before. Now whole series will 
be delayed until USB is sorted out.

Best regards,
Jernej

> The whole series goes on top of v3 of Icenowy's F1C100s USB support
> series [1]. There is no real conflict, but the lctech-pi.dts file
> references the new USB DT nodes from the .dtsi.
> 
> I put a git repo with all those patches up here:
> https://github.com/apritzel/linux/commits/f1c100s-devices-v2
> 
> For a changelog see below.
> 
> [1]
> https://lore.kernel.org/linux-arm-kernel/20221106154826.6687-1-andre.przywa
> ra@arm.com/T/#t
> 
> =================
> The Allwinner F1C100s series of SoCs shares many peripherals with other
> Allwinner SoCs. Since they are compatible, we can use the existing
> drivers, and just need to enable the devices in the DT.
> 
> This series adds the I2C controllers, the PWM device, the CIR (infrared)
> device and the LRADC (aka. KEYADC, low res ADC) to the F1C100s .dtsi, so
> boards can just use them by setting 'status = "okay";'.
> 
> The only thing missing driver-wise is the IR mod clock, which was not
> modeled in our CCU driver. Patch 4/10 fixes that.
> 
> For every device there is one patch that adds the new compatible string
> to the DT binding, and another patch to add the DT node.
> 
> This has been tested on the Lctech Pi F1C200s board, by:
> - Connecting an LED to PE6, and configuring this as the PWM pin in the DT.
>   Doing a sweep on /sys/class/pwm/pwm1/duty_cycle made the LED fade out.
> - Configuring PD0/PD12 as I2C0, and letting i2c-detect find the on-board
>   NS2009 I2C chip.
> - Connecting two resistors to the "ADC" pin, and configuring them as two
>   buttons in the DT. /dev/input/event0 properly reported button presses.
> - Connecting an infrared receiver to PE11, configured as CIR.
>   ir-keytable reported key presses on a remote control.
> 
> All those (basic) tests were successful, and prove that the peripherals
> do work and are compatible.
> 
> The final three patches add the binding docs and the .dts file for the
> Lctech Pi F1C200s development board.
> 
> Please have a look and test on your hardware, if possible.
> 
> Cheers,
> Andre
> 
> Changelog v1 ... v2:
> - dropped former patch 3/9 and 8/9: already applied
> - increase register frame size in DT for PWM and LRADC
> - drop I2C1 pins from pinctroller DT node
> - increase IR mod clock mux to 2 bits
> - fix mistyped comma in vendor prefix name
> - drop unneeded mmc0 and spi0 aliases from Lctech Pi DT
> - add /omit-if-no-ref/ tag to UART1 pins
> - add ACKs and Reviewed-by tags
> 
> 
> Andre Przywara (10):
>   dt-bindings: pwm: allwinner,sun4i-a10: Add F1C100s compatible
>   ARM: dts: suniv: f1c100s: add PWM node
>   ARM: dts: suniv: f1c100s: add I2C DT nodes
>   clk: sunxi-ng: f1c100s: Add IR mod clock
>   dt-bindings: media: IR: Add F1C100s IR compatible string
>   ARM: dts: suniv: f1c100s: add CIR DT node
>   ARM: dts: suniv: f1c100s: add LRADC node
>   dt-bindings: vendor-prefixes: add Lctech name
>   dt-bindings: arm: sunxi: add compatible strings for Lctech Pi
>   ARM: dts: suniv: Add Lctech Pi F1C200s devicetree
> 
>  .../devicetree/bindings/arm/sunxi.yaml        |  6 ++
>  .../media/allwinner,sun4i-a10-ir.yaml         |  1 +
>  .../bindings/pwm/allwinner,sun4i-a10-pwm.yaml |  4 +-
>  .../devicetree/bindings/vendor-prefixes.yaml  |  2 +
>  arch/arm/boot/dts/Makefile                    |  1 +
>  arch/arm/boot/dts/suniv-f1c100s.dtsi          | 76 ++++++++++++++++++
>  arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts | 78 +++++++++++++++++++
>  drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c      | 11 ++-
>  drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h      |  2 +-
>  include/dt-bindings/clock/suniv-ccu-f1c100s.h |  2 +
>  10 files changed, 180 insertions(+), 3 deletions(-)
>  create mode 100644 arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts
> 
> --
> 2.35.5

Re: [PATCH v2 00/10] ARM: dts: suniv: F1C100s: add more peripherals

[Andre Przywara]

On Mon, 07 Nov 2022 20:33:47 +0100
Jernej Škrabec <jernej.skrabec@gmail.com> wrote:

Hi Jernej,

thanks for the reviews!

> Dne ponedeljek, 07. november 2022 ob 01:54:23 CET je Andre Przywara 
> napisal(a):
> > This is a fixed version of the initial post. I dropped the two patches
> > that were already applied by the respective maintainers, and fixed the
> > smaller issues mentioned in the review.
> > This adds v2 of the series enabling the "Lctech Pi F1C200s" board on top,
> > also with the comments addressed.  
> 
> Please don't combine series if not agreed upon before. Now whole series will 
> be delayed until USB is sorted out.

Apologies for that. Indeed I should have added the board DT to the USB
series instead, as there is no dependency to anything in here.

If you don't mind, I will send a v3 with the last three patches
dropped, and the ACKs and R-b's added (and that one line in the commit
message fixed).

Cheers,
Andre

> 
> Best regards,
> Jernej
> 
> > The whole series goes on top of v3 of Icenowy's F1C100s USB support
> > series [1]. There is no real conflict, but the lctech-pi.dts file
> > references the new USB DT nodes from the .dtsi.
> > 
> > I put a git repo with all those patches up here:
> > https://github.com/apritzel/linux/commits/f1c100s-devices-v2
> > 
> > For a changelog see below.
> > 
> > [1]
> > https://lore.kernel.org/linux-arm-kernel/20221106154826.6687-1-andre.przywa
> > ra@arm.com/T/#t
> > 
> > =================
> > The Allwinner F1C100s series of SoCs shares many peripherals with other
> > Allwinner SoCs. Since they are compatible, we can use the existing
> > drivers, and just need to enable the devices in the DT.
> > 
> > This series adds the I2C controllers, the PWM device, the CIR (infrared)
> > device and the LRADC (aka. KEYADC, low res ADC) to the F1C100s .dtsi, so
> > boards can just use them by setting 'status = "okay";'.
> > 
> > The only thing missing driver-wise is the IR mod clock, which was not
> > modeled in our CCU driver. Patch 4/10 fixes that.
> > 
> > For every device there is one patch that adds the new compatible string
> > to the DT binding, and another patch to add the DT node.
> > 
> > This has been tested on the Lctech Pi F1C200s board, by:
> > - Connecting an LED to PE6, and configuring this as the PWM pin in the DT.
> >   Doing a sweep on /sys/class/pwm/pwm1/duty_cycle made the LED fade out.
> > - Configuring PD0/PD12 as I2C0, and letting i2c-detect find the on-board
> >   NS2009 I2C chip.
> > - Connecting two resistors to the "ADC" pin, and configuring them as two
> >   buttons in the DT. /dev/input/event0 properly reported button presses.
> > - Connecting an infrared receiver to PE11, configured as CIR.
> >   ir-keytable reported key presses on a remote control.
> > 
> > All those (basic) tests were successful, and prove that the peripherals
> > do work and are compatible.
> > 
> > The final three patches add the binding docs and the .dts file for the
> > Lctech Pi F1C200s development board.
> > 
> > Please have a look and test on your hardware, if possible.
> > 
> > Cheers,
> > Andre
> > 
> > Changelog v1 ... v2:
> > - dropped former patch 3/9 and 8/9: already applied
> > - increase register frame size in DT for PWM and LRADC
> > - drop I2C1 pins from pinctroller DT node
> > - increase IR mod clock mux to 2 bits
> > - fix mistyped comma in vendor prefix name
> > - drop unneeded mmc0 and spi0 aliases from Lctech Pi DT
> > - add /omit-if-no-ref/ tag to UART1 pins
> > - add ACKs and Reviewed-by tags
> > 
> > 
> > Andre Przywara (10):
> >   dt-bindings: pwm: allwinner,sun4i-a10: Add F1C100s compatible
> >   ARM: dts: suniv: f1c100s: add PWM node
> >   ARM: dts: suniv: f1c100s: add I2C DT nodes
> >   clk: sunxi-ng: f1c100s: Add IR mod clock
> >   dt-bindings: media: IR: Add F1C100s IR compatible string
> >   ARM: dts: suniv: f1c100s: add CIR DT node
> >   ARM: dts: suniv: f1c100s: add LRADC node
> >   dt-bindings: vendor-prefixes: add Lctech name
> >   dt-bindings: arm: sunxi: add compatible strings for Lctech Pi
> >   ARM: dts: suniv: Add Lctech Pi F1C200s devicetree
> > 
> >  .../devicetree/bindings/arm/sunxi.yaml        |  6 ++
> >  .../media/allwinner,sun4i-a10-ir.yaml         |  1 +
> >  .../bindings/pwm/allwinner,sun4i-a10-pwm.yaml |  4 +-
> >  .../devicetree/bindings/vendor-prefixes.yaml  |  2 +
> >  arch/arm/boot/dts/Makefile                    |  1 +
> >  arch/arm/boot/dts/suniv-f1c100s.dtsi          | 76 ++++++++++++++++++
> >  arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts | 78 +++++++++++++++++++
> >  drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c      | 11 ++-
> >  drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h      |  2 +-
> >  include/dt-bindings/clock/suniv-ccu-f1c100s.h |  2 +
> >  10 files changed, 180 insertions(+), 3 deletions(-)
> >  create mode 100644 arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts
> > 
> > --
> > 2.35.5  
> 
> 

Re: [PATCH v2 00/10] ARM: dts: suniv: F1C100s: add more peripherals

[Jernej Škrabec]

Dne torek, 15. november 2022 ob 01:28:08 CET je Andre Przywara napisal(a):
> On Mon, 07 Nov 2022 20:33:47 +0100
> Jernej Škrabec <jernej.skrabec@gmail.com> wrote:
> 
> Hi Jernej,
> 
> thanks for the reviews!
> 
> > Dne ponedeljek, 07. november 2022 ob 01:54:23 CET je Andre Przywara
> > 
> > napisal(a):
> > > This is a fixed version of the initial post. I dropped the two patches
> > > that were already applied by the respective maintainers, and fixed the
> > > smaller issues mentioned in the review.
> > > This adds v2 of the series enabling the "Lctech Pi F1C200s" board on
> > > top,
> > > also with the comments addressed.
> > 
> > Please don't combine series if not agreed upon before. Now whole series
> > will be delayed until USB is sorted out.
> 
> Apologies for that. Indeed I should have added the board DT to the USB
> series instead, as there is no dependency to anything in here.
> 
> If you don't mind, I will send a v3 with the last three patches
> dropped, and the ACKs and R-b's added (and that one line in the commit
> message fixed).

That would be nice. I was planning to merge other patches anyway if USB series 
is not sorted out in time, but I prefer merging whole series at once. I should 
add that to previous response, sorry.

Best regards,
Jernej

> 
> Cheers,
> Andre
> 
> > Best regards,
> > Jernej
> > 
> > > The whole series goes on top of v3 of Icenowy's F1C100s USB support
> > > series [1]. There is no real conflict, but the lctech-pi.dts file
> > > references the new USB DT nodes from the .dtsi.
> > > 
> > > I put a git repo with all those patches up here:
> > > https://github.com/apritzel/linux/commits/f1c100s-devices-v2
> > > 
> > > For a changelog see below.
> > > 
> > > [1]
> > > https://lore.kernel.org/linux-arm-kernel/20221106154826.6687-1-andre.prz
> > > ywa
> > > ra@arm.com/T/#t
> > > 
> > > =================
> > > The Allwinner F1C100s series of SoCs shares many peripherals with other
> > > Allwinner SoCs. Since they are compatible, we can use the existing
> > > drivers, and just need to enable the devices in the DT.
> > > 
> > > This series adds the I2C controllers, the PWM device, the CIR (infrared)
> > > device and the LRADC (aka. KEYADC, low res ADC) to the F1C100s .dtsi, so
> > > boards can just use them by setting 'status = "okay";'.
> > > 
> > > The only thing missing driver-wise is the IR mod clock, which was not
> > > modeled in our CCU driver. Patch 4/10 fixes that.
> > > 
> > > For every device there is one patch that adds the new compatible string
> > > to the DT binding, and another patch to add the DT node.
> > > 
> > > This has been tested on the Lctech Pi F1C200s board, by:
> > > - Connecting an LED to PE6, and configuring this as the PWM pin in the
> > > DT.
> > > 
> > >   Doing a sweep on /sys/class/pwm/pwm1/duty_cycle made the LED fade out.
> > > 
> > > - Configuring PD0/PD12 as I2C0, and letting i2c-detect find the on-board
> > > 
> > >   NS2009 I2C chip.
> > > 
> > > - Connecting two resistors to the "ADC" pin, and configuring them as two
> > > 
> > >   buttons in the DT. /dev/input/event0 properly reported button presses.
> > > 
> > > - Connecting an infrared receiver to PE11, configured as CIR.
> > > 
> > >   ir-keytable reported key presses on a remote control.
> > > 
> > > All those (basic) tests were successful, and prove that the peripherals
> > > do work and are compatible.
> > > 
> > > The final three patches add the binding docs and the .dts file for the
> > > Lctech Pi F1C200s development board.
> > > 
> > > Please have a look and test on your hardware, if possible.
> > > 
> > > Cheers,
> > > Andre
> > > 
> > > Changelog v1 ... v2:
> > > - dropped former patch 3/9 and 8/9: already applied
> > > - increase register frame size in DT for PWM and LRADC
> > > - drop I2C1 pins from pinctroller DT node
> > > - increase IR mod clock mux to 2 bits
> > > - fix mistyped comma in vendor prefix name
> > > - drop unneeded mmc0 and spi0 aliases from Lctech Pi DT
> > > - add /omit-if-no-ref/ tag to UART1 pins
> > > - add ACKs and Reviewed-by tags
> > > 
> > > Andre Przywara (10):
> > >   dt-bindings: pwm: allwinner,sun4i-a10: Add F1C100s compatible
> > >   ARM: dts: suniv: f1c100s: add PWM node
> > >   ARM: dts: suniv: f1c100s: add I2C DT nodes
> > >   clk: sunxi-ng: f1c100s: Add IR mod clock
> > >   dt-bindings: media: IR: Add F1C100s IR compatible string
> > >   ARM: dts: suniv: f1c100s: add CIR DT node
> > >   ARM: dts: suniv: f1c100s: add LRADC node
> > >   dt-bindings: vendor-prefixes: add Lctech name
> > >   dt-bindings: arm: sunxi: add compatible strings for Lctech Pi
> > >   ARM: dts: suniv: Add Lctech Pi F1C200s devicetree
> > >  
> > >  .../devicetree/bindings/arm/sunxi.yaml        |  6 ++
> > >  .../media/allwinner,sun4i-a10-ir.yaml         |  1 +
> > >  .../bindings/pwm/allwinner,sun4i-a10-pwm.yaml |  4 +-
> > >  .../devicetree/bindings/vendor-prefixes.yaml  |  2 +
> > >  arch/arm/boot/dts/Makefile                    |  1 +
> > >  arch/arm/boot/dts/suniv-f1c100s.dtsi          | 76 ++++++++++++++++++
> > >  arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts | 78 +++++++++++++++++++
> > >  drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c      | 11 ++-
> > >  drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h      |  2 +-
> > >  include/dt-bindings/clock/suniv-ccu-f1c100s.h |  2 +
> > >  10 files changed, 180 insertions(+), 3 deletions(-)
> > >  create mode 100644 arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts
> > > 
> > > --
> > > 2.35.5

Re: Re: [PATCH v2 00/10] ARM: dts: suniv: F1C100s: add more peripherals

[Jernej Škrabec]

Dne torek, 15. november 2022 ob 06:11:25 CET je Jernej Škrabec napisal(a):
> Dne torek, 15. november 2022 ob 01:28:08 CET je Andre Przywara napisal(a):
> > On Mon, 07 Nov 2022 20:33:47 +0100
> > Jernej Škrabec <jernej.skrabec@gmail.com> wrote:
> > 
> > Hi Jernej,
> > 
> > thanks for the reviews!
> > 
> > > Dne ponedeljek, 07. november 2022 ob 01:54:23 CET je Andre Przywara
> > > 
> > > napisal(a):
> > > > This is a fixed version of the initial post. I dropped the two patches
> > > > that were already applied by the respective maintainers, and fixed the
> > > > smaller issues mentioned in the review.
> > > > This adds v2 of the series enabling the "Lctech Pi F1C200s" board on
> > > > top,
> > > > also with the comments addressed.
> > > 
> > > Please don't combine series if not agreed upon before. Now whole series
> > > will be delayed until USB is sorted out.
> > 
> > Apologies for that. Indeed I should have added the board DT to the USB
> > series instead, as there is no dependency to anything in here.
> > 
> > If you don't mind, I will send a v3 with the last three patches
> > dropped, and the ACKs and R-b's added (and that one line in the commit
> > message fixed).
> 
> That would be nice. I was planning to merge other patches anyway if USB
> series is not sorted out in time, but I prefer merging whole series at
> once. I should add that to previous response, sorry.

I went ahead and merged patches 1-7, with message fix in patch 3.

Best regards,
Jernej

> 
> Best regards,
> Jernej
> 
> > Cheers,
> > Andre
> > 
> > > Best regards,
> > > Jernej
> > > 
> > > > The whole series goes on top of v3 of Icenowy's F1C100s USB support
> > > > series [1]. There is no real conflict, but the lctech-pi.dts file
> > > > references the new USB DT nodes from the .dtsi.
> > > > 
> > > > I put a git repo with all those patches up here:
> > > > https://github.com/apritzel/linux/commits/f1c100s-devices-v2
> > > > 
> > > > For a changelog see below.
> > > > 
> > > > [1]
> > > > https://lore.kernel.org/linux-arm-kernel/20221106154826.6687-1-andre.p
> > > > rz
> > > > ywa
> > > > ra@arm.com/T/#t
> > > > 
> > > > =================
> > > > The Allwinner F1C100s series of SoCs shares many peripherals with
> > > > other
> > > > Allwinner SoCs. Since they are compatible, we can use the existing
> > > > drivers, and just need to enable the devices in the DT.
> > > > 
> > > > This series adds the I2C controllers, the PWM device, the CIR
> > > > (infrared)
> > > > device and the LRADC (aka. KEYADC, low res ADC) to the F1C100s .dtsi,
> > > > so
> > > > boards can just use them by setting 'status = "okay";'.
> > > > 
> > > > The only thing missing driver-wise is the IR mod clock, which was not
> > > > modeled in our CCU driver. Patch 4/10 fixes that.
> > > > 
> > > > For every device there is one patch that adds the new compatible
> > > > string
> > > > to the DT binding, and another patch to add the DT node.
> > > > 
> > > > This has been tested on the Lctech Pi F1C200s board, by:
> > > > - Connecting an LED to PE6, and configuring this as the PWM pin in the
> > > > DT.
> > > > 
> > > >   Doing a sweep on /sys/class/pwm/pwm1/duty_cycle made the LED fade
> > > >   out.
> > > > 
> > > > - Configuring PD0/PD12 as I2C0, and letting i2c-detect find the
> > > > on-board
> > > > 
> > > >   NS2009 I2C chip.
> > > > 
> > > > - Connecting two resistors to the "ADC" pin, and configuring them as
> > > > two
> > > > 
> > > >   buttons in the DT. /dev/input/event0 properly reported button
> > > >   presses.
> > > > 
> > > > - Connecting an infrared receiver to PE11, configured as CIR.
> > > > 
> > > >   ir-keytable reported key presses on a remote control.
> > > > 
> > > > All those (basic) tests were successful, and prove that the
> > > > peripherals
> > > > do work and are compatible.
> > > > 
> > > > The final three patches add the binding docs and the .dts file for the
> > > > Lctech Pi F1C200s development board.
> > > > 
> > > > Please have a look and test on your hardware, if possible.
> > > > 
> > > > Cheers,
> > > > Andre
> > > > 
> > > > Changelog v1 ... v2:
> > > > - dropped former patch 3/9 and 8/9: already applied
> > > > - increase register frame size in DT for PWM and LRADC
> > > > - drop I2C1 pins from pinctroller DT node
> > > > - increase IR mod clock mux to 2 bits
> > > > - fix mistyped comma in vendor prefix name
> > > > - drop unneeded mmc0 and spi0 aliases from Lctech Pi DT
> > > > - add /omit-if-no-ref/ tag to UART1 pins
> > > > - add ACKs and Reviewed-by tags
> > > > 
> > > > Andre Przywara (10):
> > > >   dt-bindings: pwm: allwinner,sun4i-a10: Add F1C100s compatible
> > > >   ARM: dts: suniv: f1c100s: add PWM node
> > > >   ARM: dts: suniv: f1c100s: add I2C DT nodes
> > > >   clk: sunxi-ng: f1c100s: Add IR mod clock
> > > >   dt-bindings: media: IR: Add F1C100s IR compatible string
> > > >   ARM: dts: suniv: f1c100s: add CIR DT node
> > > >   ARM: dts: suniv: f1c100s: add LRADC node
> > > >   dt-bindings: vendor-prefixes: add Lctech name
> > > >   dt-bindings: arm: sunxi: add compatible strings for Lctech Pi
> > > >   ARM: dts: suniv: Add Lctech Pi F1C200s devicetree
> > > >  
> > > >  .../devicetree/bindings/arm/sunxi.yaml        |  6 ++
> > > >  .../media/allwinner,sun4i-a10-ir.yaml         |  1 +
> > > >  .../bindings/pwm/allwinner,sun4i-a10-pwm.yaml |  4 +-
> > > >  .../devicetree/bindings/vendor-prefixes.yaml  |  2 +
> > > >  arch/arm/boot/dts/Makefile                    |  1 +
> > > >  arch/arm/boot/dts/suniv-f1c100s.dtsi          | 76 ++++++++++++++++++
> > > >  arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts | 78
> > > >  +++++++++++++++++++
> > > >  drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c      | 11 ++-
> > > >  drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h      |  2 +-
> > > >  include/dt-bindings/clock/suniv-ccu-f1c100s.h |  2 +
> > > >  10 files changed, 180 insertions(+), 3 deletions(-)
> > > >  create mode 100644 arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts
> > > > 
> > > > --
> > > > 2.35.5