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Fri, 18 Nov 2022 04:01:32 -0600 Received: from ubuntu (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with SMTP id 2AIA1FvG074625; Fri, 18 Nov 2022 04:01:17 -0600 Date: Fri, 18 Nov 2022 02:01:14 -0800 From: Matt Ranostay To: Vaishnav Achath CC: , , , , , , Subject: Re: [PATCH v5 3/8] arm64: dts: ti: k3-j721s2-mcu-wakeup: Add support of OSPI Message-ID: References: <20221103044125.172864-1-mranostay@ti.com> <20221103044125.172864-4-mranostay@ti.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Wed, Nov 16, 2022 at 02:03:25PM +0530, Vaishnav Achath wrote: > > > On 03/11/22 10:11, Matt Ranostay wrote: > > From: Aswath Govindraju > > > > Add support for two instance of OSPI in J721S2 SoC. > > > > Cc: Vignesh Raghavendra > > Cc: Nishanth Menon > > Signed-off-by: Aswath Govindraju > > Signed-off-by: Matt Ranostay > > --- > > .../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 40 +++++++++++++++++++ > > 1 file changed, 40 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi > > index 3264b8e8faea..034122be2ed5 100644 > > --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi > > +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi > > @@ -306,4 +306,44 @@ cpts@3d000 { > > ti,cpts-periodic-outputs = <2>; > > }; > > }; > > + > > + fss: syscon@47000000 { > > + compatible = "syscon", "simple-mfd"; > > Looks like the update here to add "ti,j721e-system-controller" compatible is in > PATCH 6/8, it could have been in the same patch here instead of editing the same > node again in the series. > Will fix in next revision. - Matt > > + reg = <0x0 0x47000000 0x0 0x100>; > > + #address-cells = <2>; > > + #size-cells = <2>; > > + ranges; > > + > > + ospi0: spi@47040000 { > > + compatible = "ti,am654-ospi", "cdns,qspi-nor"; > > + reg = <0x00 0x47040000 0x00 0x100>, > > + <0x5 0x0000000 0x1 0x0000000>; > > + interrupts = ; > > + cdns,fifo-depth = <256>; > > + cdns,fifo-width = <4>; > > + cdns,trigger-address = <0x0>; > > + clocks = <&k3_clks 109 5>; > > + assigned-clocks = <&k3_clks 109 5>; > > + assigned-clock-parents = <&k3_clks 109 7>; > > + assigned-clock-rates = <166666666>; > > + power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + }; > > + > > + ospi1: spi@47050000 { > > + compatible = "ti,am654-ospi", "cdns,qspi-nor"; > > + reg = <0x00 0x47050000 0x00 0x100>, > > + <0x7 0x0000000 0x1 0x0000000>; > > + interrupts = ; > > + cdns,fifo-depth = <256>; > > + cdns,fifo-width = <4>; > > + cdns,trigger-address = <0x0>; > > + clocks = <&k3_clks 110 5>; > > + power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + }; > > + > > + }; > > }; > > Reviewed-by: Vaishnav Achath > > -- > Regards, > Vaishnav