* [PATCH v6 1/8] arm64: dts: ti: k3-j721s2-main: Add support for USB
2022-11-19 4:08 [PATCH v6 0/8] J721S2: Add support for additional IPs Matt Ranostay
@ 2022-11-19 4:08 ` Matt Ranostay
2022-11-19 4:09 ` [PATCH v6 2/8] arm64: dts: ti: k3-j721s2-main: Add SERDES and WIZ device tree node Matt Ranostay
` (7 subsequent siblings)
8 siblings, 0 replies; 15+ messages in thread
From: Matt Ranostay @ 2022-11-19 4:08 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh+dt, krzysztof.kozlowski+dt,
s-vadapalli, r-gunasekaran
Cc: linux-arm-kernel, devicetree, linux-kernel
From: Aswath Govindraju <a-govindraju@ti.com>
Add support for single instance of USB 3.0 controller in J721S2 SoC.
Reviewed-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Matt Ranostay <mranostay@ti.com>
---
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 42 ++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index 8915132efcc1..b4869bff4f22 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -26,6 +26,20 @@ l3cache-sram@200000 {
};
};
+ scm_conf: syscon@104000 {
+ compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
+ reg = <0x00 0x00104000 0x00 0x18000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00 0x00 0x00104000 0x18000>;
+
+ usb_serdes_mux: mux-controller-0 {
+ compatible = "mmio-mux";
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
+ };
+ };
+
gic500: interrupt-controller@1800000 {
compatible = "arm,gic-v3";
#address-cells = <2>;
@@ -745,6 +759,34 @@ cpts@310d0000 {
};
};
+ usbss0: cdns-usb@4104000 {
+ compatible = "ti,j721e-usb";
+ reg = <0x00 0x04104000 0x00 0x100>;
+ clocks = <&k3_clks 360 16>, <&k3_clks 360 15>;
+ clock-names = "ref", "lpm";
+ assigned-clocks = <&k3_clks 360 16>; /* USB2_REFCLK */
+ assigned-clock-parents = <&k3_clks 360 17>;
+ power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ dma-coherent;
+
+ usb0: usb@6000000 {
+ compatible = "cdns,usb3";
+ reg = <0x00 0x06000000 0x00 0x10000>,
+ <0x00 0x06010000 0x00 0x10000>,
+ <0x00 0x06020000 0x00 0x10000>;
+ reg-names = "otg", "xhci", "dev";
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "host", "peripheral", "otg";
+ maximum-speed = "super-speed";
+ dr_mode = "otg";
+ };
+ };
+
main_mcan0: can@2701000 {
compatible = "bosch,m_can";
reg = <0x00 0x02701000 0x00 0x200>,
--
2.38.GIT
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v6 2/8] arm64: dts: ti: k3-j721s2-main: Add SERDES and WIZ device tree node
2022-11-19 4:08 [PATCH v6 0/8] J721S2: Add support for additional IPs Matt Ranostay
2022-11-19 4:08 ` [PATCH v6 1/8] arm64: dts: ti: k3-j721s2-main: Add support for USB Matt Ranostay
@ 2022-11-19 4:09 ` Matt Ranostay
2022-11-22 6:26 ` Ravi Gunasekaran
2022-11-19 4:09 ` [PATCH v6 3/8] arm64: dts: ti: k3-j721s2-mcu-wakeup: Add support of OSPI Matt Ranostay
` (6 subsequent siblings)
8 siblings, 1 reply; 15+ messages in thread
From: Matt Ranostay @ 2022-11-19 4:09 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh+dt, krzysztof.kozlowski+dt,
s-vadapalli, r-gunasekaran
Cc: linux-arm-kernel, devicetree, linux-kernel
Add dt node for the single instance of WIZ (SERDES wrapper) and
SERDES module shared by PCIe, eDP and USB.
Signed-off-by: Matt Ranostay <mranostay@ti.com>
---
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 54 ++++++++++++++++++++++
1 file changed, 54 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index b4869bff4f22..adbb172658b9 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -5,6 +5,17 @@
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
*/
+#include <dt-bindings/phy/phy-cadence.h>
+#include <dt-bindings/phy/phy-ti.h>
+
+/ {
+ serdes_refclk: clock-cmnrefclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+};
+
&cbass_main {
msmc_ram: sram@70000000 {
compatible = "mmio-sram";
@@ -38,6 +49,13 @@ usb_serdes_mux: mux-controller-0 {
#mux-control-cells = <1>;
mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
};
+
+ serdes_ln_ctrl: mux-controller-80 {
+ compatible = "mmio-mux";
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */
+ <0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */
+ };
};
gic500: interrupt-controller@1800000 {
@@ -787,6 +805,42 @@ usb0: usb@6000000 {
};
};
+ serdes_wiz0: wiz@5060000 {
+ compatible = "ti,am64-wiz-10g";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 365 0>, <&k3_clks 365 3>, <&serdes_refclk>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+ num-lanes = <4>;
+ #reset-cells = <1>;
+ #clock-cells = <1>;
+ ranges = <0x5060000 0x0 0x5060000 0x10000>;
+
+ assigned-clocks = <&k3_clks 365 3>;
+ assigned-clock-parents = <&k3_clks 365 7>;
+
+ serdes0: serdes@5060000 {
+ compatible = "ti,j721e-serdes-10g";
+ reg = <0x05060000 0x00010000>;
+ reg-names = "torrent_phy";
+ resets = <&serdes_wiz0 0>;
+ reset-names = "torrent_reset";
+ clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
+ clock-names = "refclk", "phy_en_refclk";
+ assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
+ assigned-clock-parents = <&k3_clks 365 3>,
+ <&k3_clks 365 3>,
+ <&k3_clks 365 3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <1>;
+ };
+ };
+
main_mcan0: can@2701000 {
compatible = "bosch,m_can";
reg = <0x00 0x02701000 0x00 0x200>,
--
2.38.GIT
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v6 2/8] arm64: dts: ti: k3-j721s2-main: Add SERDES and WIZ device tree node
2022-11-19 4:09 ` [PATCH v6 2/8] arm64: dts: ti: k3-j721s2-main: Add SERDES and WIZ device tree node Matt Ranostay
@ 2022-11-22 6:26 ` Ravi Gunasekaran
0 siblings, 0 replies; 15+ messages in thread
From: Ravi Gunasekaran @ 2022-11-22 6:26 UTC (permalink / raw)
To: Matt Ranostay, nm, vigneshr, kristo, robh+dt,
krzysztof.kozlowski+dt, s-vadapalli
Cc: linux-arm-kernel, devicetree, linux-kernel
On 19/11/22 9:39 am, Matt Ranostay wrote:
> Add dt node for the single instance of WIZ (SERDES wrapper) and
> SERDES module shared by PCIe, eDP and USB.
>
> Signed-off-by: Matt Ranostay <mranostay@ti.com>
> ---
> arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 54 ++++++++++++++++++++++
> 1 file changed, 54 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> index b4869bff4f22..adbb172658b9 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> @@ -5,6 +5,17 @@
> * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
> */
>
> +#include <dt-bindings/phy/phy-cadence.h>
> +#include <dt-bindings/phy/phy-ti.h>
> +
> +/ {
> + serdes_refclk: clock-cmnrefclk {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <0>;
> + };
> +};
> +
> &cbass_main {
> msmc_ram: sram@70000000 {
> compatible = "mmio-sram";
> @@ -38,6 +49,13 @@ usb_serdes_mux: mux-controller-0 {
> #mux-control-cells = <1>;
> mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
> };
> +
> + serdes_ln_ctrl: mux-controller-80 {
> + compatible = "mmio-mux";
> + #mux-control-cells = <1>;
> + mux-reg-masks = <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */
> + <0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */
> + };
> };
>
> gic500: interrupt-controller@1800000 {
> @@ -787,6 +805,42 @@ usb0: usb@6000000 {
> };
> };
>
> + serdes_wiz0: wiz@5060000 {
> + compatible = "ti,am64-wiz-10g";
Using compatible "ti,am64-wiz-10g" may cause issues as the wiz_data->type plays a role in serdes configuration
Please relook into this
> + #address-cells = <1>;
> + #size-cells = <1>;
> + power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 365 0>, <&k3_clks 365 3>, <&serdes_refclk>;
> + clock-names = "fck", "core_ref_clk", "ext_ref_clk";
> + num-lanes = <4>;
> + #reset-cells = <1>;
> + #clock-cells = <1>;
> + ranges = <0x5060000 0x0 0x5060000 0x10000>;
> +
> + assigned-clocks = <&k3_clks 365 3>;
> + assigned-clock-parents = <&k3_clks 365 7>;
> +
> + serdes0: serdes@5060000 {
> + compatible = "ti,j721e-serdes-10g";
> + reg = <0x05060000 0x00010000>;
> + reg-names = "torrent_phy";
> + resets = <&serdes_wiz0 0>;
> + reset-names = "torrent_reset";
> + clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
> + <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
> + clock-names = "refclk", "phy_en_refclk";
> + assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
> + <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
> + <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
> + assigned-clock-parents = <&k3_clks 365 3>,
> + <&k3_clks 365 3>,
> + <&k3_clks 365 3>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #clock-cells = <1>;
> + };
> + };
> +
> main_mcan0: can@2701000 {
> compatible = "bosch,m_can";
> reg = <0x00 0x02701000 0x00 0x200>,
--
Regards,
Ravi
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v6 3/8] arm64: dts: ti: k3-j721s2-mcu-wakeup: Add support of OSPI
2022-11-19 4:08 [PATCH v6 0/8] J721S2: Add support for additional IPs Matt Ranostay
2022-11-19 4:08 ` [PATCH v6 1/8] arm64: dts: ti: k3-j721s2-main: Add support for USB Matt Ranostay
2022-11-19 4:09 ` [PATCH v6 2/8] arm64: dts: ti: k3-j721s2-main: Add SERDES and WIZ device tree node Matt Ranostay
@ 2022-11-19 4:09 ` Matt Ranostay
2022-11-21 16:53 ` Andrew Davis
2022-11-19 4:09 ` [PATCH v6 4/8] arm64: dts: ti: k3-j721s2-common-proc-board: Enable SERDES0 Matt Ranostay
` (5 subsequent siblings)
8 siblings, 1 reply; 15+ messages in thread
From: Matt Ranostay @ 2022-11-19 4:09 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh+dt, krzysztof.kozlowski+dt,
s-vadapalli, r-gunasekaran
Cc: linux-arm-kernel, devicetree, linux-kernel
From: Aswath Govindraju <a-govindraju@ti.com>
Add support for two instance of OSPI in J721S2 SoC.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Matt Ranostay <mranostay@ti.com>
---
.../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 40 +++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
index 0af242aa9816..46b3aab93c4b 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
@@ -306,4 +306,44 @@ cpts@3d000 {
ti,cpts-periodic-outputs = <2>;
};
};
+
+ fss: syscon@47000000 {
+ compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
+ reg = <0x00 0x47000000 0x00 0x100>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ ospi0: spi@47040000 {
+ compatible = "ti,am654-ospi", "cdns,qspi-nor";
+ reg = <0x00 0x47040000 0x00 0x100>,
+ <0x5 0x0000000 0x1 0x0000000>;
+ interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
+ cdns,fifo-depth = <256>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x0>;
+ clocks = <&k3_clks 109 5>;
+ assigned-clocks = <&k3_clks 109 5>;
+ assigned-clock-parents = <&k3_clks 109 7>;
+ assigned-clock-rates = <166666666>;
+ power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ ospi1: spi@47050000 {
+ compatible = "ti,am654-ospi", "cdns,qspi-nor";
+ reg = <0x00 0x47050000 0x00 0x100>,
+ <0x7 0x0000000 0x1 0x0000000>;
+ interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>;
+ cdns,fifo-depth = <256>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x0>;
+ clocks = <&k3_clks 110 5>;
+ power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ };
};
--
2.38.GIT
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v6 3/8] arm64: dts: ti: k3-j721s2-mcu-wakeup: Add support of OSPI
2022-11-19 4:09 ` [PATCH v6 3/8] arm64: dts: ti: k3-j721s2-mcu-wakeup: Add support of OSPI Matt Ranostay
@ 2022-11-21 16:53 ` Andrew Davis
2022-11-22 3:16 ` Matt Ranostay
0 siblings, 1 reply; 15+ messages in thread
From: Andrew Davis @ 2022-11-21 16:53 UTC (permalink / raw)
To: Matt Ranostay, nm, vigneshr, kristo, robh+dt,
krzysztof.kozlowski+dt, s-vadapalli, r-gunasekaran
Cc: linux-arm-kernel, devicetree, linux-kernel
On 11/18/22 10:09 PM, Matt Ranostay wrote:
> From: Aswath Govindraju <a-govindraju@ti.com>
>
> Add support for two instance of OSPI in J721S2 SoC.
>
> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
> Signed-off-by: Matt Ranostay <mranostay@ti.com>
> ---
> .../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 40 +++++++++++++++++++
> 1 file changed, 40 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
> index 0af242aa9816..46b3aab93c4b 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
> @@ -306,4 +306,44 @@ cpts@3d000 {
> ti,cpts-periodic-outputs = <2>;
> };
> };
> +
> + fss: syscon@47000000 {
> + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
This node is not the "ti,j721e-system-controller", and those don't have
SPI nodes in the binding, so this will have failed the dtbs_check anyway..
Should be just a "simple-bus".
Andrew
> + reg = <0x00 0x47000000 0x00 0x100>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + ospi0: spi@47040000 {
> + compatible = "ti,am654-ospi", "cdns,qspi-nor";
> + reg = <0x00 0x47040000 0x00 0x100>,
> + <0x5 0x0000000 0x1 0x0000000>;
> + interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
> + cdns,fifo-depth = <256>;
> + cdns,fifo-width = <4>;
> + cdns,trigger-address = <0x0>;
> + clocks = <&k3_clks 109 5>;
> + assigned-clocks = <&k3_clks 109 5>;
> + assigned-clock-parents = <&k3_clks 109 7>;
> + assigned-clock-rates = <166666666>;
> + power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + ospi1: spi@47050000 {
> + compatible = "ti,am654-ospi", "cdns,qspi-nor";
> + reg = <0x00 0x47050000 0x00 0x100>,
> + <0x7 0x0000000 0x1 0x0000000>;
> + interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>;
> + cdns,fifo-depth = <256>;
> + cdns,fifo-width = <4>;
> + cdns,trigger-address = <0x0>;
> + clocks = <&k3_clks 110 5>;
> + power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + };
> };
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v6 3/8] arm64: dts: ti: k3-j721s2-mcu-wakeup: Add support of OSPI
2022-11-21 16:53 ` Andrew Davis
@ 2022-11-22 3:16 ` Matt Ranostay
0 siblings, 0 replies; 15+ messages in thread
From: Matt Ranostay @ 2022-11-22 3:16 UTC (permalink / raw)
To: Andrew Davis
Cc: nm, vigneshr, kristo, robh+dt, krzysztof.kozlowski+dt,
s-vadapalli, r-gunasekaran, linux-arm-kernel, devicetree,
linux-kernel
On Mon, Nov 21, 2022 at 10:53:03AM -0600, Andrew Davis wrote:
> On 11/18/22 10:09 PM, Matt Ranostay wrote:
> > From: Aswath Govindraju <a-govindraju@ti.com>
> >
> > Add support for two instance of OSPI in J721S2 SoC.
> >
> > Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
> > Signed-off-by: Matt Ranostay <mranostay@ti.com>
> > ---
> > .../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 40 +++++++++++++++++++
> > 1 file changed, 40 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
> > index 0af242aa9816..46b3aab93c4b 100644
> > --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
> > +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
> > @@ -306,4 +306,44 @@ cpts@3d000 {
> > ti,cpts-periodic-outputs = <2>;
> > };
> > };
> > +
> > + fss: syscon@47000000 {
> > + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
>
> This node is not the "ti,j721e-system-controller", and those don't have
> SPI nodes in the binding, so this will have failed the dtbs_check anyway..
>
> Should be just a "simple-bus".
>
> Andrew
>
Noted for next revision.
Thanks,
Matt
> > + reg = <0x00 0x47000000 0x00 0x100>;
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
> > +
> > + ospi0: spi@47040000 {
> > + compatible = "ti,am654-ospi", "cdns,qspi-nor";
> > + reg = <0x00 0x47040000 0x00 0x100>,
> > + <0x5 0x0000000 0x1 0x0000000>;
> > + interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
> > + cdns,fifo-depth = <256>;
> > + cdns,fifo-width = <4>;
> > + cdns,trigger-address = <0x0>;
> > + clocks = <&k3_clks 109 5>;
> > + assigned-clocks = <&k3_clks 109 5>;
> > + assigned-clock-parents = <&k3_clks 109 7>;
> > + assigned-clock-rates = <166666666>;
> > + power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
> > +
> > + ospi1: spi@47050000 {
> > + compatible = "ti,am654-ospi", "cdns,qspi-nor";
> > + reg = <0x00 0x47050000 0x00 0x100>,
> > + <0x7 0x0000000 0x1 0x0000000>;
> > + interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>;
> > + cdns,fifo-depth = <256>;
> > + cdns,fifo-width = <4>;
> > + cdns,trigger-address = <0x0>;
> > + clocks = <&k3_clks 110 5>;
> > + power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
> > +
> > + };
> > };
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v6 4/8] arm64: dts: ti: k3-j721s2-common-proc-board: Enable SERDES0
2022-11-19 4:08 [PATCH v6 0/8] J721S2: Add support for additional IPs Matt Ranostay
` (2 preceding siblings ...)
2022-11-19 4:09 ` [PATCH v6 3/8] arm64: dts: ti: k3-j721s2-mcu-wakeup: Add support of OSPI Matt Ranostay
@ 2022-11-19 4:09 ` Matt Ranostay
2022-11-19 4:09 ` [PATCH v6 5/8] arm64: dts: ti: k3-j721s2-common-proc-board: Add USB support Matt Ranostay
` (4 subsequent siblings)
8 siblings, 0 replies; 15+ messages in thread
From: Matt Ranostay @ 2022-11-19 4:09 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh+dt, krzysztof.kozlowski+dt,
s-vadapalli, r-gunasekaran
Cc: linux-arm-kernel, devicetree, linux-kernel
From: Aswath Govindraju <a-govindraju@ti.com>
Configure first lane to PCIe, the second lane to USB and the last two lanes
to eDP. Also, add sub-nodes to SERDES0 DT node to represent SERDES0 is
connected to PCIe.
Reviewed-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Matt Ranostay <mranostay@ti.com>
---
.../dts/ti/k3-j721s2-common-proc-board.dts | 22 +++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
index a7aa6cf08acd..c3a397484c70 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
@@ -9,6 +9,9 @@
#include "k3-j721s2-som-p0.dtsi"
#include <dt-bindings/net/ti-dp83867.h>
+#include <dt-bindings/phy/phy-cadence.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/mux/ti-serdes.h>
/ {
compatible = "ti,j721s2-evm", "ti,j721s2";
@@ -296,6 +299,25 @@ &cpsw_port1 {
phy-handle = <&phy0>;
};
+&serdes_ln_ctrl {
+ idle-states = <J721S2_SERDES0_LANE0_PCIE1_LANE0>, <J721S2_SERDES0_LANE1_USB>,
+ <J721S2_SERDES0_LANE2_EDP_LANE2>, <J721S2_SERDES0_LANE3_EDP_LANE3>;
+};
+
+&serdes_refclk {
+ clock-frequency = <100000000>;
+};
+
+&serdes0 {
+ serdes0_pcie_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ resets = <&serdes_wiz0 1>;
+ };
+};
+
&mcu_mcan0 {
status = "okay";
pinctrl-names = "default";
--
2.38.GIT
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v6 5/8] arm64: dts: ti: k3-j721s2-common-proc-board: Add USB support
2022-11-19 4:08 [PATCH v6 0/8] J721S2: Add support for additional IPs Matt Ranostay
` (3 preceding siblings ...)
2022-11-19 4:09 ` [PATCH v6 4/8] arm64: dts: ti: k3-j721s2-common-proc-board: Enable SERDES0 Matt Ranostay
@ 2022-11-19 4:09 ` Matt Ranostay
2022-11-19 4:09 ` [PATCH v6 6/8] arm64: dts: ti: k3-j721s2: Add support for OSPI Flashes Matt Ranostay
` (3 subsequent siblings)
8 siblings, 0 replies; 15+ messages in thread
From: Matt Ranostay @ 2022-11-19 4:09 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh+dt, krzysztof.kozlowski+dt,
s-vadapalli, r-gunasekaran
Cc: linux-arm-kernel, devicetree, linux-kernel
From: Aswath Govindraju <a-govindraju@ti.com>
The board uses lane 1 of SERDES for USB. Set the mux
accordingly.
The USB controller and EVM supports super-speed for USB0
on the Type-C port. However, the SERDES has a limitation
that upto 2 protocols can be used at a time. The SERDES is
wired for PCIe, eDP and USB super-speed. It has been
chosen to use PCIe and eDP as default. So restrict
USB0 to high-speed mode.
Reviewed-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Matt Ranostay <mranostay@ti.com>
---
.../dts/ti/k3-j721s2-common-proc-board.dts | 22 +++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
index c3a397484c70..c787d46f89de 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
@@ -147,6 +147,12 @@ vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
J721S2_IOPAD(0x020, PIN_INPUT, 7) /* (AA23) MCAN15_RX.GPIO0_8 */
>;
};
+
+ main_usbss0_pins_default: main-usbss0-pins-default {
+ pinctrl-single,pins = <
+ J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */
+ >;
+ };
};
&wkup_pmx0 {
@@ -318,6 +324,22 @@ serdes0_pcie_link: phy@0 {
};
};
+&usb_serdes_mux {
+ idle-states = <1>; /* USB0 to SERDES lane 1 */
+};
+
+&usbss0 {
+ pinctrl-0 = <&main_usbss0_pins_default>;
+ pinctrl-names = "default";
+ ti,vbus-divider;
+ ti,usb2-only;
+};
+
+&usb0 {
+ dr_mode = "otg";
+ maximum-speed = "high-speed";
+};
+
&mcu_mcan0 {
status = "okay";
pinctrl-names = "default";
--
2.38.GIT
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v6 6/8] arm64: dts: ti: k3-j721s2: Add support for OSPI Flashes
2022-11-19 4:08 [PATCH v6 0/8] J721S2: Add support for additional IPs Matt Ranostay
` (4 preceding siblings ...)
2022-11-19 4:09 ` [PATCH v6 5/8] arm64: dts: ti: k3-j721s2-common-proc-board: Add USB support Matt Ranostay
@ 2022-11-19 4:09 ` Matt Ranostay
2022-11-19 4:09 ` [PATCH v6 7/8] arm64: dts: ti: k3-j721s2-main: Add PCIe device tree node Matt Ranostay
` (2 subsequent siblings)
8 siblings, 0 replies; 15+ messages in thread
From: Matt Ranostay @ 2022-11-19 4:09 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh+dt, krzysztof.kozlowski+dt,
s-vadapalli, r-gunasekaran
Cc: linux-arm-kernel, devicetree, linux-kernel
From: Aswath Govindraju <a-govindraju@ti.com>
J721S2 has an OSPI NOR flash on its SOM connected the OSPI0 instance and a
QSPI NOR flash on the common processor board connected to the OSPI1
instance. Add support for the same
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Matt Ranostay <mranostay@ti.com>
---
.../dts/ti/k3-j721s2-common-proc-board.dts | 34 +++++++++++++++
arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 42 +++++++++++++++++++
2 files changed, 76 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
index c787d46f89de..0503e690cfaf 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
@@ -206,6 +206,20 @@ mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-pins-default {
J721S2_WKUP_IOPAD(0x0c8, PIN_INPUT, 7) /* (C28) WKUP_GPIO0_2 */
>;
};
+
+ mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x040, PIN_OUTPUT, 0) /* (A19) MCU_OSPI1_CLK */
+ J721S2_WKUP_IOPAD(0x05c, PIN_OUTPUT, 0) /* (D20) MCU_OSPI1_CSn0 */
+ J721S2_WKUP_IOPAD(0x060, PIN_OUTPUT, 0) /* (C21) MCU_OSPI1_CSn1 */
+ J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (D21) MCU_OSPI1_D0 */
+ J721S2_WKUP_IOPAD(0x050, PIN_INPUT, 0) /* (G20) MCU_OSPI1_D1 */
+ J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (C20) MCU_OSPI1_D2 */
+ J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */
+ J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */
+ J721S2_WKUP_IOPAD(0x044, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */
+ >;
+ };
};
&main_gpio2 {
@@ -340,6 +354,26 @@ &usb0 {
maximum-speed = "high-speed";
};
+&ospi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
+
+ flash@0{
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <40000000>;
+ cdns,tshsl-ns = <60>;
+ cdns,tsd2d-ns = <60>;
+ cdns,tchsh-ns = <60>;
+ cdns,tslch-ns = <60>;
+ cdns,read-delay = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+};
+
&mcu_mcan0 {
status = "okay";
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi
index 6930efff8a5a..2ffea00e19d7 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi
@@ -39,6 +39,28 @@ transceiver0: can-phy0 {
};
};
+&wkup_pmx0 {
+ mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */
+ J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */
+ J721S2_WKUP_IOPAD(0x030, PIN_OUTPUT, 0) /* (G17) MCU_OSPI0_CSn1 */
+ J721S2_WKUP_IOPAD(0x038, PIN_OUTPUT, 0) /* (F14) MCU_OSPI0_CSn2 */
+ J721S2_WKUP_IOPAD(0x03c, PIN_OUTPUT, 0) /* (F17) MCU_OSPI0_CSn3 */
+ J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */
+ J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */
+ J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */
+ J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (F18) MCU_OSPI0_D3 */
+ J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (E19) MCU_OSPI0_D4 */
+ J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D5 */
+ J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (F19) MCU_OSPI0_D6 */
+ J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */
+ J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */
+ J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI0_LBCLKO */
+ >;
+ };
+};
+
&main_pmx0 {
main_i2c0_pins_default: main-i2c0-pins-default {
pinctrl-single,pins = <
@@ -79,3 +101,23 @@ &main_mcan16 {
pinctrl-names = "default";
phys = <&transceiver0>;
};
+
+&ospi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ spi-tx-bus-width = <8>;
+ spi-rx-bus-width = <8>;
+ spi-max-frequency = <25000000>;
+ cdns,tshsl-ns = <60>;
+ cdns,tsd2d-ns = <60>;
+ cdns,tchsh-ns = <60>;
+ cdns,tslch-ns = <60>;
+ cdns,read-delay = <4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+};
--
2.38.GIT
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v6 7/8] arm64: dts: ti: k3-j721s2-main: Add PCIe device tree node
2022-11-19 4:08 [PATCH v6 0/8] J721S2: Add support for additional IPs Matt Ranostay
` (5 preceding siblings ...)
2022-11-19 4:09 ` [PATCH v6 6/8] arm64: dts: ti: k3-j721s2: Add support for OSPI Flashes Matt Ranostay
@ 2022-11-19 4:09 ` Matt Ranostay
2022-11-21 17:12 ` Andrew Davis
2022-11-19 4:09 ` [PATCH v6 8/8] arm64: dts: ti: k3-j721s2-common-proc-board: Enable PCIe Matt Ranostay
2022-11-21 16:49 ` [PATCH v6 0/8] J721S2: Add support for additional IPs Roger Quadros
8 siblings, 1 reply; 15+ messages in thread
From: Matt Ranostay @ 2022-11-19 4:09 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh+dt, krzysztof.kozlowski+dt,
s-vadapalli, r-gunasekaran
Cc: linux-arm-kernel, devicetree, linux-kernel
From: Aswath Govindraju <a-govindraju@ti.com>
Add PCIe device tree node (both RC and EP) for the single PCIe
instance present in j721s2.
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Matt Ranostay <mranostay@ti.com>
---
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 61 ++++++++++++++++++++++
1 file changed, 61 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index adbb172658b9..04294e25d587 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -841,6 +841,67 @@ serdes0: serdes@5060000 {
};
};
+ pcie1_rc: pcie@2910000 {
+ compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host";
+ reg = <0x00 0x02910000 0x00 0x1000>,
+ <0x00 0x02917000 0x00 0x400>,
+ <0x00 0x0d800000 0x00 0x00800000>,
+ <0x00 0x18000000 0x00 0x00001000>;
+ reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
+ interrupt-names = "link_state";
+ interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
+ device_type = "pci";
+ ti,syscon-pcie-ctrl = <&scm_conf 0x074>;
+ max-link-speed = <3>;
+ num-lanes = <4>;
+ power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 276 41>;
+ clock-names = "fck";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x0 0xff>;
+ vendor-id = <0x104c>;
+ device-id = <0xb013>;
+ msi-map = <0x0 &gic_its 0x0 0x10000>;
+ dma-coherent;
+ ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>,
+ <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>;
+ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */
+ <0 0 0 2 &pcie1_intc 0>, /* INT B */
+ <0 0 0 3 &pcie1_intc 0>, /* INT C */
+ <0 0 0 4 &pcie1_intc 0>; /* INT D */
+
+ pcie1_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 324 IRQ_TYPE_EDGE_RISING>;
+ };
+ };
+
+ pcie1_ep: pcie-ep@2910000 {
+ compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep";
+ reg = <0x00 0x02910000 0x00 0x1000>,
+ <0x00 0x02917000 0x00 0x400>,
+ <0x00 0x0d800000 0x00 0x00800000>,
+ <0x00 0x18000000 0x00 0x08000000>;
+ reg-names = "intd_cfg", "user_cfg", "reg", "mem";
+ interrupt-names = "link_state";
+ interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
+ ti,syscon-pcie-ctrl = <&scm_conf 0x074>;
+ max-link-speed = <3>;
+ num-lanes = <4>;
+ power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 276 41>;
+ clock-names = "fck";
+ max-functions = /bits/ 8 <6>;
+ max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
+ dma-coherent;
+ };
+
main_mcan0: can@2701000 {
compatible = "bosch,m_can";
reg = <0x00 0x02701000 0x00 0x200>,
--
2.38.GIT
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v6 7/8] arm64: dts: ti: k3-j721s2-main: Add PCIe device tree node
2022-11-19 4:09 ` [PATCH v6 7/8] arm64: dts: ti: k3-j721s2-main: Add PCIe device tree node Matt Ranostay
@ 2022-11-21 17:12 ` Andrew Davis
2022-11-22 3:13 ` Matt Ranostay
0 siblings, 1 reply; 15+ messages in thread
From: Andrew Davis @ 2022-11-21 17:12 UTC (permalink / raw)
To: Matt Ranostay, nm, vigneshr, kristo, robh+dt,
krzysztof.kozlowski+dt, s-vadapalli, r-gunasekaran
Cc: linux-arm-kernel, devicetree, linux-kernel
On 11/18/22 10:09 PM, Matt Ranostay wrote:
> From: Aswath Govindraju <a-govindraju@ti.com>
>
> Add PCIe device tree node (both RC and EP) for the single PCIe
> instance present in j721s2.
>
So which is it, you have two nodes but this is one device. It can
switch between the two modes, a property should have been used to
select the mode for the device.
Making two nodes for the same device as examples of what they could
look like, then only enabling one of the two in the board level DT
is not how this is done anywhere else. Take the common parts and
make one node here with those. Then at the board level .dts where we
select what mode this driver will act in, add the specific bits for
the chosen mode.
Andrew
> Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
> Signed-off-by: Matt Ranostay <mranostay@ti.com>
> ---
> arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 61 ++++++++++++++++++++++
> 1 file changed, 61 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> index adbb172658b9..04294e25d587 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> @@ -841,6 +841,67 @@ serdes0: serdes@5060000 {
> };
> };
>
> + pcie1_rc: pcie@2910000 {
> + compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host";
> + reg = <0x00 0x02910000 0x00 0x1000>,
> + <0x00 0x02917000 0x00 0x400>,
> + <0x00 0x0d800000 0x00 0x00800000>,
> + <0x00 0x18000000 0x00 0x00001000>;
> + reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
> + interrupt-names = "link_state";
> + interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
> + device_type = "pci";
> + ti,syscon-pcie-ctrl = <&scm_conf 0x074>;
> + max-link-speed = <3>;
> + num-lanes = <4>;
> + power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 276 41>;
> + clock-names = "fck";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + bus-range = <0x0 0xff>;
> + vendor-id = <0x104c>;
> + device-id = <0xb013>;
> + msi-map = <0x0 &gic_its 0x0 0x10000>;
> + dma-coherent;
> + ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>,
> + <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>;
> + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */
> + <0 0 0 2 &pcie1_intc 0>, /* INT B */
> + <0 0 0 3 &pcie1_intc 0>, /* INT C */
> + <0 0 0 4 &pcie1_intc 0>; /* INT D */
> +
> + pcie1_intc: interrupt-controller {
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + interrupt-parent = <&gic500>;
> + interrupts = <GIC_SPI 324 IRQ_TYPE_EDGE_RISING>;
> + };
> + };
> +
> + pcie1_ep: pcie-ep@2910000 {
> + compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep";
> + reg = <0x00 0x02910000 0x00 0x1000>,
> + <0x00 0x02917000 0x00 0x400>,
> + <0x00 0x0d800000 0x00 0x00800000>,
> + <0x00 0x18000000 0x00 0x08000000>;
> + reg-names = "intd_cfg", "user_cfg", "reg", "mem";
> + interrupt-names = "link_state";
> + interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
> + ti,syscon-pcie-ctrl = <&scm_conf 0x074>;
> + max-link-speed = <3>;
> + num-lanes = <4>;
> + power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 276 41>;
> + clock-names = "fck";
> + max-functions = /bits/ 8 <6>;
> + max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
> + dma-coherent;
> + };
> +
> main_mcan0: can@2701000 {
> compatible = "bosch,m_can";
> reg = <0x00 0x02701000 0x00 0x200>,
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v6 7/8] arm64: dts: ti: k3-j721s2-main: Add PCIe device tree node
2022-11-21 17:12 ` Andrew Davis
@ 2022-11-22 3:13 ` Matt Ranostay
0 siblings, 0 replies; 15+ messages in thread
From: Matt Ranostay @ 2022-11-22 3:13 UTC (permalink / raw)
To: Andrew Davis
Cc: nm, vigneshr, kristo, robh+dt, krzysztof.kozlowski+dt,
s-vadapalli, r-gunasekaran, linux-arm-kernel, devicetree,
linux-kernel
On Mon, Nov 21, 2022 at 11:12:18AM -0600, Andrew Davis wrote:
> On 11/18/22 10:09 PM, Matt Ranostay wrote:
> > From: Aswath Govindraju <a-govindraju@ti.com>
> >
> > Add PCIe device tree node (both RC and EP) for the single PCIe
> > instance present in j721s2.
> >
>
> So which is it, you have two nodes but this is one device. It can
> switch between the two modes, a property should have been used to
> select the mode for the device.
>
> Making two nodes for the same device as examples of what they could
> look like, then only enabling one of the two in the board level DT
> is not how this is done anywhere else. Take the common parts and
> make one node here with those. Then at the board level .dts where we
> select what mode this driver will act in, add the specific bits for
> the chosen mode.
>
This isn't how it is done in k3-j7200-common-proc-board.dts and k3-j7200-main.dtsi
Now I'm fine with making it common node if that is way to go..
- Matt
> Andrew
>
> > Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> > Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
> > Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
> > Signed-off-by: Matt Ranostay <mranostay@ti.com>
> > ---
> > arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 61 ++++++++++++++++++++++
> > 1 file changed, 61 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> > index adbb172658b9..04294e25d587 100644
> > --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> > +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> > @@ -841,6 +841,67 @@ serdes0: serdes@5060000 {
> > };
> > };
> > + pcie1_rc: pcie@2910000 {
> > + compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host";
> > + reg = <0x00 0x02910000 0x00 0x1000>,
> > + <0x00 0x02917000 0x00 0x400>,
> > + <0x00 0x0d800000 0x00 0x00800000>,
> > + <0x00 0x18000000 0x00 0x00001000>;
> > + reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
> > + interrupt-names = "link_state";
> > + interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
> > + device_type = "pci";
> > + ti,syscon-pcie-ctrl = <&scm_conf 0x074>;
> > + max-link-speed = <3>;
> > + num-lanes = <4>;
> > + power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
> > + clocks = <&k3_clks 276 41>;
> > + clock-names = "fck";
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > + bus-range = <0x0 0xff>;
> > + vendor-id = <0x104c>;
> > + device-id = <0xb013>;
> > + msi-map = <0x0 &gic_its 0x0 0x10000>;
> > + dma-coherent;
> > + ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>,
> > + <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>;
> > + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
> > + #interrupt-cells = <1>;
> > + interrupt-map-mask = <0 0 0 7>;
> > + interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */
> > + <0 0 0 2 &pcie1_intc 0>, /* INT B */
> > + <0 0 0 3 &pcie1_intc 0>, /* INT C */
> > + <0 0 0 4 &pcie1_intc 0>; /* INT D */
> > +
> > + pcie1_intc: interrupt-controller {
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > + interrupt-parent = <&gic500>;
> > + interrupts = <GIC_SPI 324 IRQ_TYPE_EDGE_RISING>;
> > + };
> > + };
> > +
> > + pcie1_ep: pcie-ep@2910000 {
> > + compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep";
> > + reg = <0x00 0x02910000 0x00 0x1000>,
> > + <0x00 0x02917000 0x00 0x400>,
> > + <0x00 0x0d800000 0x00 0x00800000>,
> > + <0x00 0x18000000 0x00 0x08000000>;
> > + reg-names = "intd_cfg", "user_cfg", "reg", "mem";
> > + interrupt-names = "link_state";
> > + interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
> > + ti,syscon-pcie-ctrl = <&scm_conf 0x074>;
> > + max-link-speed = <3>;
> > + num-lanes = <4>;
> > + power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
> > + clocks = <&k3_clks 276 41>;
> > + clock-names = "fck";
> > + max-functions = /bits/ 8 <6>;
> > + max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
> > + dma-coherent;
> > + };
> > +
> > main_mcan0: can@2701000 {
> > compatible = "bosch,m_can";
> > reg = <0x00 0x02701000 0x00 0x200>,
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v6 8/8] arm64: dts: ti: k3-j721s2-common-proc-board: Enable PCIe
2022-11-19 4:08 [PATCH v6 0/8] J721S2: Add support for additional IPs Matt Ranostay
` (6 preceding siblings ...)
2022-11-19 4:09 ` [PATCH v6 7/8] arm64: dts: ti: k3-j721s2-main: Add PCIe device tree node Matt Ranostay
@ 2022-11-19 4:09 ` Matt Ranostay
2022-11-21 16:49 ` [PATCH v6 0/8] J721S2: Add support for additional IPs Roger Quadros
8 siblings, 0 replies; 15+ messages in thread
From: Matt Ranostay @ 2022-11-19 4:09 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh+dt, krzysztof.kozlowski+dt,
s-vadapalli, r-gunasekaran
Cc: linux-arm-kernel, devicetree, linux-kernel
From: Aswath Govindraju <a-govindraju@ti.com>
x1 lane PCIe slot in the common processor board is enabled and connected to
J721S2 SOM. Add PCIe DT node in common processor board to reflect the
same.
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Matt Ranostay <mranostay@ti.com>
---
.../boot/dts/ti/k3-j721s2-common-proc-board.dts | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
index 0503e690cfaf..862611784ab3 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
@@ -374,6 +374,20 @@ flash@0{
};
};
+&pcie1_rc {
+ reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
+ phys = <&serdes0_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <1>;
+};
+
+&pcie1_ep {
+ phys = <&serdes0_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <1>;
+ status = "disabled";
+};
+
&mcu_mcan0 {
status = "okay";
pinctrl-names = "default";
--
2.38.GIT
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v6 0/8] J721S2: Add support for additional IPs
2022-11-19 4:08 [PATCH v6 0/8] J721S2: Add support for additional IPs Matt Ranostay
` (7 preceding siblings ...)
2022-11-19 4:09 ` [PATCH v6 8/8] arm64: dts: ti: k3-j721s2-common-proc-board: Enable PCIe Matt Ranostay
@ 2022-11-21 16:49 ` Roger Quadros
8 siblings, 0 replies; 15+ messages in thread
From: Roger Quadros @ 2022-11-21 16:49 UTC (permalink / raw)
To: Matt Ranostay, nm, vigneshr, kristo, robh+dt,
krzysztof.kozlowski+dt, s-vadapalli, r-gunasekaran
Cc: linux-arm-kernel, devicetree, linux-kernel
On 19/11/2022 06:08, Matt Ranostay wrote:
> The following series of patches add support for the following
> on J721S2 common processor board,
>
> - USB
> - SerDes
> - OSPI
> - PCIe
>
> Changes from v1:
> * Resolve issues with dt schema reporting
> * Minor changes related to consistency on node naming and value
>
> Changes from v2:
> * Added PCIe RC + EP enablement patchsets
> * Added device-id for j722s2 PCIe host in dt documentation
> * Reworked SERDES + WIZ enablement patchset to use properies for clocks
> defines versus entire devicetree nodes. Results in cleaner code that
> doesn't break dt-schema or the driver functionality.
>
> Changes from v3:
> * Rebased changes on top of '[PATCH 00/12] TI J7x Disable Incomplete DT Nodes'
> * Removed "dt-bindings: PCI: Add host mode device-id for j721s2 platform" patch and
> send it own series to avoid a dependency that would hold up other patches in this
> series
>
> Changes from v4:
> * Add my Signed-off-by lines to all patchsets
>
> Changes from v5:
> * Removed Cc from commit messages to reduce clutter
> * Squashed changes for device tree nodes that get modified latter in the patchset
> series
>
> Aswath Govindraju (7):
> arm64: dts: ti: k3-j721s2-main: Add support for USB
> arm64: dts: ti: k3-j721s2-mcu-wakeup: Add support of OSPI
> arm64: dts: ti: k3-j721s2-common-proc-board: Enable SERDES0
> arm64: dts: ti: k3-j721s2-common-proc-board: Add USB support
> arm64: dts: ti: k3-j721s2: Add support for OSPI Flashes
> arm64: dts: ti: k3-j721s2-main: Add PCIe device tree node
> arm64: dts: ti: k3-j721s2-common-proc-board: Enable PCIe
>
> Matt Ranostay (1):
> arm64: dts: ti: k3-j721s2-main: Add SERDES and WIZ device tree node
>
> .../dts/ti/k3-j721s2-common-proc-board.dts | 92 ++++++++++
> arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 157 ++++++++++++++++++
> .../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 40 +++++
> arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 42 +++++
> 4 files changed, 331 insertions(+)
>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
--
cheers,
-roger
^ permalink raw reply [flat|nested] 15+ messages in thread