From: Conor Dooley <conor.dooley@microchip.com>
To: Anup Patel <apatel@ventanamicro.com>
Cc: Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>,
Andrew Jones <ajones@ventanamicro.com>,
Atish Patra <atishp@atishpatra.org>,
Samuel Holland <samuel@sholland.org>,
Anup Patel <anup@brainfault.org>, <devicetree@vger.kernel.org>,
<linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v3 3/3] clocksource: timer-riscv: Set CLOCK_EVT_FEAT_C3STOP based on DT
Date: Fri, 25 Nov 2022 13:13:04 +0000 [thread overview]
Message-ID: <Y4C/YOoHxX5dxwG3@wendy> (raw)
In-Reply-To: <20221125112105.427045-4-apatel@ventanamicro.com>
On Fri, Nov 25, 2022 at 04:51:05PM +0530, Anup Patel wrote:
> We should set CLOCK_EVT_FEAT_C3STOP for a clock_event_device only
> when riscv,timer-cant-wake-up DT property is present in the RISC-V
> timer DT node.
>
> This way CLOCK_EVT_FEAT_C3STOP feature is set for clock_event_device
> based on RISC-V platform capabilities rather than having it set for
> all RISC-V platforms.
I need to go do some testing on what setting the C3STOP flag does on
platforms other than PolarFire SoC. I'm not sure that we should be
enabling this flag *at all* until we know that it does not break on
other platforms too.
Hopefully I'll get to it tonight or tomorrow..
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
> drivers/clocksource/timer-riscv.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
> index a0d66fabf073..0c8bdd168a45 100644
> --- a/drivers/clocksource/timer-riscv.c
> +++ b/drivers/clocksource/timer-riscv.c
> @@ -28,6 +28,7 @@
> #include <asm/timex.h>
>
> static DEFINE_STATIC_KEY_FALSE(riscv_sstc_available);
> +static bool riscv_timer_cant_wake_cpu;
>
> static int riscv_clock_next_event(unsigned long delta,
> struct clock_event_device *ce)
> @@ -85,6 +86,8 @@ static int riscv_timer_starting_cpu(unsigned int cpu)
>
> ce->cpumask = cpumask_of(cpu);
> ce->irq = riscv_clock_event_irq;
> + if (riscv_timer_cant_wake_cpu)
> + ce->features |= CLOCK_EVT_FEAT_C3STOP;
> clockevents_config_and_register(ce, riscv_timebase, 100, 0x7fffffff);
>
> enable_percpu_irq(riscv_clock_event_irq,
> @@ -139,6 +142,13 @@ static int __init riscv_timer_init_dt(struct device_node *n)
> if (cpuid != smp_processor_id())
> return 0;
>
> + child = of_find_compatible_node(NULL, NULL, "riscv,timer");
> + if (child) {
> + riscv_timer_cant_wake_cpu = of_property_read_bool(child,
> + "riscv,timer-cant-wake-cpu");
> + of_node_put(child);
> + }
> +
> domain = NULL;
> child = of_get_compatible_child(n, "riscv,cpu-intc");
> if (!child) {
> --
> 2.34.1
>
next prev parent reply other threads:[~2022-11-25 13:13 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-25 11:21 [PATCH v3 0/3] Improve CLOCK_EVT_FEAT_C3STOP feature setting Anup Patel
2022-11-25 11:21 ` [PATCH v3 1/3] Revert "clocksource/drivers/riscv: Events are stopped during CPU suspend" Anup Patel
2022-11-25 11:21 ` [PATCH v3 2/3] dt-bindings: timer: Add bindings for the RISC-V timer device Anup Patel
2022-11-25 13:09 ` Conor Dooley
2022-11-25 13:48 ` Anup Patel
2022-11-25 23:57 ` Conor Dooley
2022-11-25 11:21 ` [PATCH v3 3/3] clocksource: timer-riscv: Set CLOCK_EVT_FEAT_C3STOP based on DT Anup Patel
2022-11-25 13:13 ` Conor Dooley [this message]
2022-11-25 23:44 ` Conor Dooley
2022-11-26 14:51 ` Conor Dooley
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