From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 29F80C43217 for ; Fri, 25 Nov 2022 12:25:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229877AbiKYMZr (ORCPT ); Fri, 25 Nov 2022 07:25:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50110 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229580AbiKYMZe (ORCPT ); Fri, 25 Nov 2022 07:25:34 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 31AB0450AC; Fri, 25 Nov 2022 04:25:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1669379133; x=1700915133; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=1MH4WmgIg0ZlYvyJXa/5tJQIPZf6/zpnA84EQYEbUiY=; b=I71gNujIcpCa85on50Gw8CVKvthmEtnpQ2ZYV3+WQlI5Sn+88HblYAf4 eDqd6yUsmgW1J1JBvEr4JSErIiAV/smLBF2eQeLOsnGH/z3NwdAoT5E17 9oxRUeWqo/WrrH0F62XznoCfdhv2ma//rVz347j2GwHfTjvZXQIqqgLWx oSXfGufW3afVrZg7HtjxvKZ7WOUpAkKXD1fXCSJCjIpc1rs9bObZyvA1E sYGG1vAxCAQFpVJKfvQAy+TdE2USayKP75u9Bsjeum53VKVQ3Hm/U8rJb 1f8fAn1XMLR2P33rXa4dH6IlZ97hIO00F4pYxVuRiUcoPY2+NU6jH2NPp w==; X-IronPort-AV: E=Sophos;i="5.96,193,1665471600"; d="scan'208";a="185169434" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 25 Nov 2022 05:25:32 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 25 Nov 2022 05:25:31 -0700 Received: from wendy (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12 via Frontend Transport; Fri, 25 Nov 2022 05:25:28 -0700 Date: Fri, 25 Nov 2022 12:25:10 +0000 From: Conor Dooley To: Krzysztof Kozlowski CC: "Lad, Prabhakar" , Paul Walmsley , Palmer Dabbelt , Albert Ou , Geert Uytterhoeven , Magnus Damm , Heiko Stuebner , Rob Herring , Krzysztof Kozlowski , Guo Ren , Jisheng Zhang , Atish Patra , Anup Patel , Andrew Jones , Nathan Chancellor , Philipp Tomsich , , , , , Biju Das , Lad Prabhakar Subject: Re: [PATCH v4 6/7] dt-bindings: cache: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller Message-ID: References: <20221124172207.153718-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20221124172207.153718-7-prabhakar.mahadev-lad.rj@bp.renesas.com> <70d1bfde-f57f-1741-08d3-23e362793595@linaro.org> <9b0f8312-2caa-b9f3-edf3-1b720532f559@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <9b0f8312-2caa-b9f3-edf3-1b720532f559@linaro.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Fri, Nov 25, 2022 at 01:12:18PM +0100, Krzysztof Kozlowski wrote: > On 25/11/2022 11:34, Lad, Prabhakar wrote: > >>> +/* Device, Non-bufferable */ > >>> +#define AX45MP_PMACFG_MTYP_DEV_NON_BUF (0 << 2) > >>> +/* Device, bufferable */ > >>> +#define AX45MP_PMACFG_MTYP_DEV_BUF (1 << 2) > >>> +/* Memory, Non-cacheable, Non-bufferable */ > >>> +#define AX45MP_PMACFG_MTYP_MEM_NON_CACHE_NON_BUF (2 << 2) > >>> +/* Memory, Non-cacheable, Bufferable */ > >>> +#define AX45MP_PMACFG_MTYP_MEM_NON_CACHE_BUF (3 << 2) > >> > >> What are all these? They don't look like flags, because 3 = 1 | 2... > >> they don't look like constants, because we do not use shifts in > >> constants. Are these some register values? I also do not see the header > >> being used in the code, so why having a bindings header if it is not > >> used (DTS is not usage...)? > >> > > These are register bit values for the MTYP[5:2] field. The DTS example > > in the binding doc (above) uses these macros. I haven't included the > > DTS/I patches with this patchset yet do think I should? > > Then why storing it as bindings? Bindings headers describe the interface > implemented by drivers and used by DTS, but this is not implemented by > drivers. IIUC, some of these properties are non-discoverable attributes of the cache controller. I see two things that could be done here that are "better" than #defining bits: - add an RZ/Five specific compatible and use match data to set the attributes which is only possible if the pma-regions are set on a per SoC basis - make pma-regions into a child node, in which andestech,non-cacheable andestech,non-bufferable etc are properties of the child node Prabhakar, does that make sense or am I off with my understanding of the attributes? Thanks, Conor.