From: Johan Hovold <johan@kernel.org>
To: Abel Vesa <abel.vesa@linaro.org>
Cc: Andy Gross <agross@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konrad.dybcio@linaro.org>,
"vkoul@kernel.org" <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org,
devicetree@vger.kernel.org,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 6/6] phy: qcom-qmp-ufs: Add SM8550 support
Date: Thu, 12 Jan 2023 16:29:59 +0100 [thread overview]
Message-ID: <Y8And9VVvpnSInlj@hovoldconsulting.com> (raw)
In-Reply-To: <20230112130542.1399921-7-abel.vesa@linaro.org>
On Thu, Jan 12, 2023 at 03:05:42PM +0200, Abel Vesa wrote:
> Add SM8550 specific register layout and table configs.
>
> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 100 ++++++++++++++++++++++++
> 1 file changed, 100 insertions(+)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> index 5936a3a05002..a9b666f32f59 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> @@ -95,6 +95,13 @@ static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
> [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL,
> };
>
> +static const char * const sm8550_ufs_phy_clk_l[] = {
> + "qref", "ref",
> +};
These clocks would to be added to the binding too, but based on:
https://lore.kernel.org/r/20230112135926.1572191-1-abel.vesa@linaro.org
you really don't need these at all and what you call 'qref'
(GCC_UFS_PHY_PHY_AUX_CLK) is just 'ref_aux' below.
> +
> static const char * const sdm845_ufs_phy_clk_l[] = {
> "ref", "ref_aux",
> };
> @@ -721,6 +787,15 @@ static const struct qmp_ufs_offsets qmp_ufs_offsets_v5 = {
> .rx2 = 0xa00,
> };
>
> +static const struct qmp_ufs_offsets qmp_ufs_offsets_v6 = {
> + .serdes = 0,
> + .pcs = 0x400,
Zero pad .pcs to 4 digits?
> + .tx = 0x1000,
> + .rx = 0x1200,
> + .tx2 = 0x1800,
> + .rx2 = 0x1a00,
> +};
Johan
next prev parent reply other threads:[~2023-01-12 15:39 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-12 13:05 [PATCH v2 0/6] phy: qualcomm: Add UFS support for SM8550 Abel Vesa
2023-01-12 13:05 ` [PATCH v2 1/6] dt-bindings: phy: Add QMP UFS PHY comptible " Abel Vesa
2023-01-12 14:32 ` Krzysztof Kozlowski
2023-01-12 13:05 ` [PATCH v2 2/6] phy: qcom-qmp: qserdes-com: Add v6 register offsets Abel Vesa
2023-01-12 13:05 ` [PATCH v2 3/6] phy: qcom-qmp: qserdes-txrx: " Abel Vesa
2023-01-12 13:05 ` [PATCH v2 4/6] phy: qcom-qmp: qserdes-txrx-ufs: " Abel Vesa
2023-01-12 13:05 ` [PATCH v2 5/6] phy: qcom-qmp: pcs-ufs: " Abel Vesa
2023-01-12 13:05 ` [PATCH v2 6/6] phy: qcom-qmp-ufs: Add SM8550 support Abel Vesa
2023-01-12 15:29 ` Johan Hovold [this message]
2023-01-13 18:35 ` Vinod Koul
2023-01-16 14:14 ` Abel Vesa
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