* [PATCH v2 0/6] phy: qualcomm: Add UFS support for SM8550
@ 2023-01-12 13:05 Abel Vesa
2023-01-12 13:05 ` [PATCH v2 1/6] dt-bindings: phy: Add QMP UFS PHY comptible " Abel Vesa
` (5 more replies)
0 siblings, 6 replies; 11+ messages in thread
From: Abel Vesa @ 2023-01-12 13:05 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, vkoul@kernel.org,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-msm, linux-phy, devicetree, Linux Kernel Mailing List
This patchset relies on the following two patchsets:
https://lore.kernel.org/all/20221123104443.3415267-1-dmitry.baryshkov@linaro.org/
https://lore.kernel.org/all/20221222141001.54849-2-manivannan.sadhasivam@linaro.org/
The v1 of this patchset is:
https://lore.kernel.org/all/20221116120157.2706810-1-abel.vesa@linaro.org/
Changes since v1:
* dropped all UFS unrelated patches and also register offsets
* switched to sc8280xp bindings, like Johan's suggested.
Abel Vesa (6):
dt-bindings: phy: Add QMP UFS PHY comptible for SM8550
phy: qcom-qmp: qserdes-com: Add v6 register offsets
phy: qcom-qmp: qserdes-txrx: Add v6 register offsets
phy: qcom-qmp: qserdes-txrx-ufs: Add v6 register offsets
phy: qcom-qmp: pcs-ufs: Add v6 register offsets
phy: qcom-qmp-ufs: Add SM8550 support
.../phy/qcom,sc8280xp-qmp-ufs-phy.yaml | 1 +
.../phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 31 ++++++
.../qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 82 ++++++++++++++
.../phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 30 ++++++
.../qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h | 77 ++++++++++++++
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 100 ++++++++++++++++++
drivers/phy/qualcomm/phy-qcom-qmp.h | 6 ++
7 files changed, 327 insertions(+)
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h
--
2.34.1
^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH v2 1/6] dt-bindings: phy: Add QMP UFS PHY comptible for SM8550 2023-01-12 13:05 [PATCH v2 0/6] phy: qualcomm: Add UFS support for SM8550 Abel Vesa @ 2023-01-12 13:05 ` Abel Vesa 2023-01-12 14:32 ` Krzysztof Kozlowski 2023-01-12 13:05 ` [PATCH v2 2/6] phy: qcom-qmp: qserdes-com: Add v6 register offsets Abel Vesa ` (4 subsequent siblings) 5 siblings, 1 reply; 11+ messages in thread From: Abel Vesa @ 2023-01-12 13:05 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Konrad Dybcio, vkoul@kernel.org, Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski Cc: linux-arm-msm, linux-phy, devicetree, Linux Kernel Mailing List Document the QMP UFS PHY compatible for SM8550. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> --- .../devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml index 32ed1886fbae..cd4e877415d6 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml @@ -17,6 +17,7 @@ properties: compatible: enum: - qcom,sc8280xp-qmp-ufs-phy + - qcom,sm8550-qmp-ufs-phy reg: maxItems: 1 -- 2.34.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v2 1/6] dt-bindings: phy: Add QMP UFS PHY comptible for SM8550 2023-01-12 13:05 ` [PATCH v2 1/6] dt-bindings: phy: Add QMP UFS PHY comptible " Abel Vesa @ 2023-01-12 14:32 ` Krzysztof Kozlowski 0 siblings, 0 replies; 11+ messages in thread From: Krzysztof Kozlowski @ 2023-01-12 14:32 UTC (permalink / raw) To: Abel Vesa, Andy Gross, Bjorn Andersson, Konrad Dybcio, vkoul@kernel.org, Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski Cc: linux-arm-msm, linux-phy, devicetree, Linux Kernel Mailing List On 12/01/2023 14:05, Abel Vesa wrote: > Document the QMP UFS PHY compatible for SM8550. > > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > --- Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v2 2/6] phy: qcom-qmp: qserdes-com: Add v6 register offsets 2023-01-12 13:05 [PATCH v2 0/6] phy: qualcomm: Add UFS support for SM8550 Abel Vesa 2023-01-12 13:05 ` [PATCH v2 1/6] dt-bindings: phy: Add QMP UFS PHY comptible " Abel Vesa @ 2023-01-12 13:05 ` Abel Vesa 2023-01-12 13:05 ` [PATCH v2 3/6] phy: qcom-qmp: qserdes-txrx: " Abel Vesa ` (3 subsequent siblings) 5 siblings, 0 replies; 11+ messages in thread From: Abel Vesa @ 2023-01-12 13:05 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Konrad Dybcio, vkoul@kernel.org, Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski Cc: linux-arm-msm, linux-phy, devicetree, Linux Kernel Mailing List The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB, UFS and PCIE g3x2. Add the new qserdes com offsets in a dedicated header file. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> --- .../qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 82 +++++++++++++++++++ drivers/phy/qualcomm/phy-qcom-qmp.h | 2 + 2 files changed, 84 insertions(+) create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h new file mode 100644 index 000000000000..0fdfeec98d36 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_QSERDES_COM_V6_H_ +#define QCOM_PHY_QMP_QSERDES_COM_V6_H_ + +/* Only for QMP V6 PHY - QSERDES COM registers */ + +#define QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1 0x00 +#define QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1 0x04 +#define QSERDES_V6_COM_CP_CTRL_MODE1 0x10 +#define QSERDES_V6_COM_PLL_RCTRL_MODE1 0x14 +#define QSERDES_V6_COM_PLL_CCTRL_MODE1 0x18 +#define QSERDES_V6_COM_CORECLK_DIV_MODE1 0x1c +#define QSERDES_V6_COM_LOCK_CMP1_MODE1 0x20 +#define QSERDES_V6_COM_LOCK_CMP2_MODE1 0x24 +#define QSERDES_V6_COM_DEC_START_MODE1 0x28 +#define QSERDES_V6_COM_DEC_START_MSB_MODE1 0x2c +#define QSERDES_V6_COM_DIV_FRAC_START1_MODE1 0x30 +#define QSERDES_V6_COM_DIV_FRAC_START2_MODE1 0x34 +#define QSERDES_V6_COM_DIV_FRAC_START3_MODE1 0x38 +#define QSERDES_V6_COM_HSCLK_SEL_1 0x3c +#define QSERDES_V6_COM_VCO_TUNE1_MODE1 0x48 +#define QSERDES_V6_COM_VCO_TUNE2_MODE1 0x4c +#define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x50 +#define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x54 +#define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x58 +#define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x5c +#define QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0 0x60 +#define QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0 0x64 +#define QSERDES_V6_COM_CP_CTRL_MODE0 0x70 +#define QSERDES_V6_COM_PLL_RCTRL_MODE0 0x74 +#define QSERDES_V6_COM_PLL_CCTRL_MODE0 0x78 +#define QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0 0x7c +#define QSERDES_V6_COM_LOCK_CMP1_MODE0 0x80 +#define QSERDES_V6_COM_LOCK_CMP2_MODE0 0x84 +#define QSERDES_V6_COM_DEC_START_MODE0 0x88 +#define QSERDES_V6_COM_DEC_START_MSB_MODE0 0x8c +#define QSERDES_V6_COM_DIV_FRAC_START1_MODE0 0x90 +#define QSERDES_V6_COM_DIV_FRAC_START2_MODE0 0x94 +#define QSERDES_V6_COM_DIV_FRAC_START3_MODE0 0x98 +#define QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1 0x9c +#define QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0 0xa0 +#define QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0 0xa4 +#define QSERDES_V6_COM_VCO_TUNE1_MODE0 0xa8 +#define QSERDES_V6_COM_VCO_TUNE2_MODE0 0xac +#define QSERDES_V6_COM_BG_TIMER 0xbc +#define QSERDES_V6_COM_SSC_EN_CENTER 0xc0 +#define QSERDES_V6_COM_SSC_PER1 0xcc +#define QSERDES_V6_COM_SSC_PER2 0xd0 +#define QSERDES_V6_COM_PLL_POST_DIV_MUX 0xd8 +#define QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN 0xdc +#define QSERDES_V6_COM_CLK_ENABLE1 0xe0 +#define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4 +#define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8 +#define QSERDES_V6_COM_PLL_IVCO 0xf4 +#define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110 +#define QSERDES_V6_COM_RESETSM_CNTRL 0x118 +#define QSERDES_V6_COM_LOCK_CMP_EN 0x120 +#define QSERDES_V6_COM_LOCK_CMP_CFG 0x124 +#define QSERDES_V6_COM_VCO_TUNE_CTRL 0x13c +#define QSERDES_V6_COM_VCO_TUNE_MAP 0x140 +#define QSERDES_V6_COM_VCO_TUNE_INITVAL2 0x148 +#define QSERDES_V6_COM_CLK_SELECT 0x164 +#define QSERDES_V6_COM_CORE_CLK_EN 0x170 +#define QSERDES_V6_COM_CMN_CONFIG_1 0x174 +#define QSERDES_V6_COM_SVS_MODE_CLK_SEL 0x17c +#define QSERDES_V6_COM_CMN_MISC_1 0x184 +#define QSERDES_V6_COM_CMN_MODE 0x188 +#define QSERDES_V6_COM_PLL_VCO_DC_LEVEL_CTRL 0x198 +#define QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_1 0x1a4 +#define QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_2 0x1a8 +#define QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_3 0x1ac +#define QSERDES_V6_COM_ADDITIONAL_MISC 0x1b4 +#define QSERDES_V6_COM_ADDITIONAL_MISC_2 0x1b8 +#define QSERDES_V6_COM_ADDITIONAL_MISC_3 0x1bc +#define QSERDES_V6_COM_CMN_STATUS 0x1d0 +#define QSERDES_V6_COM_C_READY_STATUS 0x1f8 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h index 29a48f0436d2..70b3bf7e5e37 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h @@ -21,6 +21,8 @@ #include "phy-qcom-qmp-qserdes-txrx-v5_20.h" #include "phy-qcom-qmp-qserdes-txrx-v5_5nm.h" +#include "phy-qcom-qmp-qserdes-com-v6.h" + #include "phy-qcom-qmp-qserdes-pll.h" #include "phy-qcom-qmp-pcs-v2.h" -- 2.34.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v2 3/6] phy: qcom-qmp: qserdes-txrx: Add v6 register offsets 2023-01-12 13:05 [PATCH v2 0/6] phy: qualcomm: Add UFS support for SM8550 Abel Vesa 2023-01-12 13:05 ` [PATCH v2 1/6] dt-bindings: phy: Add QMP UFS PHY comptible " Abel Vesa 2023-01-12 13:05 ` [PATCH v2 2/6] phy: qcom-qmp: qserdes-com: Add v6 register offsets Abel Vesa @ 2023-01-12 13:05 ` Abel Vesa 2023-01-12 13:05 ` [PATCH v2 4/6] phy: qcom-qmp: qserdes-txrx-ufs: " Abel Vesa ` (2 subsequent siblings) 5 siblings, 0 replies; 11+ messages in thread From: Abel Vesa @ 2023-01-12 13:05 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Konrad Dybcio, vkoul@kernel.org, Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski Cc: linux-arm-msm, linux-phy, devicetree, Linux Kernel Mailing List The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB, UFS and PCIE g3x2. Add the new qserdes TX RX offsets in a dedicated header file. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> --- .../qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h | 77 +++++++++++++++++++ drivers/phy/qualcomm/phy-qcom-qmp.h | 1 + 2 files changed, 78 insertions(+) create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h new file mode 100644 index 000000000000..ba45b554b6f5 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_QSERDES_TXRX_USB_V6_H_ +#define QCOM_PHY_QMP_QSERDES_TXRX_USB_V6_H_ + +#define QSERDES_V6_TX_CLKBUF_ENABLE 0x08 +#define QSERDES_V6_TX_RESET_TSYNC_EN 0x1c +#define QSERDES_V6_TX_PRE_STALL_LDO_BOOST_EN 0x20 +#define QSERDES_V6_TX_TX_BAND 0x24 +#define QSERDES_V6_TX_INTERFACE_SELECT 0x2c +#define QSERDES_V6_TX_RES_CODE_LANE_TX 0x34 +#define QSERDES_V6_TX_RES_CODE_LANE_RX 0x38 +#define QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX 0x3c +#define QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX 0x40 +#define QSERDES_V6_TX_PARRATE_REC_DETECT_IDLE_EN 0x60 +#define QSERDES_V6_TX_BIST_PATTERN7 0x7c +#define QSERDES_V6_TX_LANE_MODE_1 0x84 +#define QSERDES_V6_TX_LANE_MODE_3 0x8c +#define QSERDES_V6_TX_LANE_MODE_4 0x90 +#define QSERDES_V6_TX_LANE_MODE_5 0x94 +#define QSERDES_V6_TX_RCV_DETECT_LVL_2 0xa4 +#define QSERDES_V6_TX_TRAN_DRVR_EMP_EN 0xc0 +#define QSERDES_V6_TX_TX_INTERFACE_MODE 0xc4 +#define QSERDES_V6_TX_VMODE_CTRL1 0xc8 +#define QSERDES_V6_TX_PI_QEC_CTRL 0xe4 + +#define QSERDES_V6_RX_UCDR_FO_GAIN 0x08 +#define QSERDES_V6_RX_UCDR_SO_GAIN 0x14 +#define QSERDES_V6_RX_UCDR_FASTLOCK_FO_GAIN 0x30 +#define QSERDES_V6_RX_UCDR_SO_SATURATION_AND_ENABLE 0x34 +#define QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_LOW 0x3c +#define QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_HIGH 0x40 +#define QSERDES_V6_RX_UCDR_PI_CONTROLS 0x44 +#define QSERDES_V6_RX_UCDR_SB2_THRESH1 0x4c +#define QSERDES_V6_RX_UCDR_SB2_THRESH2 0x50 +#define QSERDES_V6_RX_UCDR_SB2_GAIN1 0x54 +#define QSERDES_V6_RX_UCDR_SB2_GAIN2 0x58 +#define QSERDES_V6_RX_AUX_DATA_TCOARSE_TFINE 0x60 +#define QSERDES_V6_RX_TX_ADAPT_POST_THRESH 0xcc +#define QSERDES_V6_RX_VGA_CAL_CNTRL1 0xd4 +#define QSERDES_V6_RX_VGA_CAL_CNTRL2 0xd8 +#define QSERDES_V6_RX_GM_CAL 0xdc +#define QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL2 0xec +#define QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL3 0xf0 +#define QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL4 0xf4 +#define QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW 0xf8 +#define QSERDES_V6_RX_RX_IDAC_TSETTLE_HIGH 0xfc +#define QSERDES_V6_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 +#define QSERDES_V6_RX_SIDGET_ENABLES 0x118 +#define QSERDES_V6_RX_SIGDET_CNTRL 0x11c +#define QSERDES_V6_RX_SIGDET_DEGLITCH_CNTRL 0x124 +#define QSERDES_V6_RX_RX_MODE_00_LOW 0x15c +#define QSERDES_V6_RX_RX_MODE_00_HIGH 0x160 +#define QSERDES_V6_RX_RX_MODE_00_HIGH2 0x164 +#define QSERDES_V6_RX_RX_MODE_00_HIGH3 0x168 +#define QSERDES_V6_RX_RX_MODE_00_HIGH4 0x16c +#define QSERDES_V6_RX_RX_MODE_01_LOW 0x170 +#define QSERDES_V6_RX_RX_MODE_01_HIGH 0x174 +#define QSERDES_V6_RX_RX_MODE_01_HIGH2 0x178 +#define QSERDES_V6_RX_RX_MODE_01_HIGH3 0x17c +#define QSERDES_V6_RX_RX_MODE_01_HIGH4 0x180 +#define QSERDES_V6_RX_RX_MODE_10_LOW 0x184 +#define QSERDES_V6_RX_RX_MODE_10_HIGH 0x188 +#define QSERDES_V6_RX_RX_MODE_10_HIGH2 0x18c +#define QSERDES_V6_RX_RX_MODE_10_HIGH3 0x190 +#define QSERDES_V6_RX_RX_MODE_10_HIGH4 0x194 +#define QSERDES_V6_RX_DFE_EN_TIMER 0x1a0 +#define QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4 +#define QSERDES_V6_RX_DCC_CTRL1 0x1a8 +#define QSERDES_V6_RX_VTH_CODE 0x1b0 +#define QSERDES_V6_RX_SIGDET_CAL_CTRL1 0x1e4 +#define QSERDES_V6_RX_SIGDET_CAL_TRIM 0x1f8 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h index 70b3bf7e5e37..62796ff5c35e 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h @@ -22,6 +22,7 @@ #include "phy-qcom-qmp-qserdes-txrx-v5_5nm.h" #include "phy-qcom-qmp-qserdes-com-v6.h" +#include "phy-qcom-qmp-qserdes-txrx-v6.h" #include "phy-qcom-qmp-qserdes-pll.h" -- 2.34.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v2 4/6] phy: qcom-qmp: qserdes-txrx-ufs: Add v6 register offsets 2023-01-12 13:05 [PATCH v2 0/6] phy: qualcomm: Add UFS support for SM8550 Abel Vesa ` (2 preceding siblings ...) 2023-01-12 13:05 ` [PATCH v2 3/6] phy: qcom-qmp: qserdes-txrx: " Abel Vesa @ 2023-01-12 13:05 ` Abel Vesa 2023-01-12 13:05 ` [PATCH v2 5/6] phy: qcom-qmp: pcs-ufs: " Abel Vesa 2023-01-12 13:05 ` [PATCH v2 6/6] phy: qcom-qmp-ufs: Add SM8550 support Abel Vesa 5 siblings, 0 replies; 11+ messages in thread From: Abel Vesa @ 2023-01-12 13:05 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Konrad Dybcio, vkoul@kernel.org, Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski Cc: linux-arm-msm, linux-phy, devicetree, Linux Kernel Mailing List The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB, UFS and PCIE g3x2. Add the new qserdes TX RX but UFS specific offsets in a dedicated header file. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> --- .../phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 30 +++++++++++++++++++ drivers/phy/qualcomm/phy-qcom-qmp.h | 1 + 2 files changed, 31 insertions(+) create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h new file mode 100644 index 000000000000..e4d38fefdf18 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_QSERDES_TXRX_UFS_V6_H_ +#define QCOM_PHY_QMP_QSERDES_TXRX_UFS_V6_H_ + +#define QSERDES_UFS_V6_TX_RES_CODE_LANE_TX 0x28 +#define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c +#define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30 +#define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34 +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0x08 +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0x10 + +#define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178 +#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208 +#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c +#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214 +#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6 0x220 +#define QSERDES_UFS_V6_RX_MODE_RATE2_B3 0x238 +#define QSERDES_UFS_V6_RX_MODE_RATE2_B6 0x244 +#define QSERDES_UFS_V6_RX_MODE_RATE3_B3 0x25c +#define QSERDES_UFS_V6_RX_MODE_RATE3_B4 0x260 +#define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264 +#define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270 +#define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280 +#define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h index 62796ff5c35e..6d6108925716 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h @@ -23,6 +23,7 @@ #include "phy-qcom-qmp-qserdes-com-v6.h" #include "phy-qcom-qmp-qserdes-txrx-v6.h" +#include "phy-qcom-qmp-qserdes-txrx-ufs-v6.h" #include "phy-qcom-qmp-qserdes-pll.h" -- 2.34.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v2 5/6] phy: qcom-qmp: pcs-ufs: Add v6 register offsets 2023-01-12 13:05 [PATCH v2 0/6] phy: qualcomm: Add UFS support for SM8550 Abel Vesa ` (3 preceding siblings ...) 2023-01-12 13:05 ` [PATCH v2 4/6] phy: qcom-qmp: qserdes-txrx-ufs: " Abel Vesa @ 2023-01-12 13:05 ` Abel Vesa 2023-01-12 13:05 ` [PATCH v2 6/6] phy: qcom-qmp-ufs: Add SM8550 support Abel Vesa 5 siblings, 0 replies; 11+ messages in thread From: Abel Vesa @ 2023-01-12 13:05 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Konrad Dybcio, vkoul@kernel.org, Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski Cc: linux-arm-msm, linux-phy, devicetree, Linux Kernel Mailing List The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB, UFS and PCIE g3x2. Add the new PCS UFS specific offsets in a dedicated header file. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> --- .../phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 31 +++++++++++++++++++ drivers/phy/qualcomm/phy-qcom-qmp.h | 2 ++ 2 files changed, 33 insertions(+) create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h new file mode 100644 index 000000000000..dde8830257b5 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_PCS_UFS_V6_H_ +#define QCOM_PHY_QMP_PCS_UFS_V6_H_ + +/* Only for QMP V6 PHY - UFS PCS registers */ +#define QPHY_V6_PCS_UFS_PHY_START 0x000 +#define QPHY_V6_PCS_UFS_POWER_DOWN_CONTROL 0x004 +#define QPHY_V6_PCS_UFS_SW_RESET 0x008 +#define QPHY_V6_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c +#define QPHY_V6_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010 +#define QPHY_V6_PCS_UFS_PLL_CNTL 0x02c +#define QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030 +#define QPHY_V6_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038 +#define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060 +#define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074 +#define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc +#define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158 +#define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c +#define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184 +#define QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2 0x18c +#define QPHY_V6_PCS_UFS_TX_PWM_GEAR_BAND 0x178 +#define QPHY_V6_PCS_UFS_TX_HS_GEAR_BAND 0x174 +#define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8 +#define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4 +#define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h index 6d6108925716..9de8e7e41af0 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h @@ -49,6 +49,8 @@ #include "phy-qcom-qmp-pcs-pcie-v5_20.h" +#include "phy-qcom-qmp-pcs-ufs-v6.h" + #include "phy-qcom-qmp-pcie-qhp.h" /* Only for QMP V3 & V4 PHY - DP COM registers */ -- 2.34.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v2 6/6] phy: qcom-qmp-ufs: Add SM8550 support 2023-01-12 13:05 [PATCH v2 0/6] phy: qualcomm: Add UFS support for SM8550 Abel Vesa ` (4 preceding siblings ...) 2023-01-12 13:05 ` [PATCH v2 5/6] phy: qcom-qmp: pcs-ufs: " Abel Vesa @ 2023-01-12 13:05 ` Abel Vesa 2023-01-12 15:29 ` Johan Hovold 2023-01-13 18:35 ` Vinod Koul 5 siblings, 2 replies; 11+ messages in thread From: Abel Vesa @ 2023-01-12 13:05 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Konrad Dybcio, vkoul@kernel.org, Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski Cc: linux-arm-msm, linux-phy, devicetree, Linux Kernel Mailing List Add SM8550 specific register layout and table configs. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 100 ++++++++++++++++++++++++ 1 file changed, 100 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index 5936a3a05002..a9b666f32f59 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -95,6 +95,13 @@ static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL, }; +static const unsigned int sm8550_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { + [QPHY_START_CTRL] = QPHY_V6_PCS_UFS_PHY_START, + [QPHY_PCS_READY_STATUS] = QPHY_V6_PCS_UFS_READY_STATUS, + [QPHY_SW_RESET] = QPHY_V6_PCS_UFS_SW_RESET, + [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_UFS_POWER_DOWN_CONTROL, +}; + static const struct qmp_phy_init_tbl msm8996_ufsphy_serdes[] = { QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7), @@ -599,6 +606,61 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_pcs[] = { QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a), }; +static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = { + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07), +}; + +static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = { + QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x05), + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07), +}; + +static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = { + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e), + + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2), + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xc2), + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6, 0x60), + + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B3, 0x9e), + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B6, 0x60), + + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B3, 0x9e), + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B4, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B5, 0x36), + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02), +}; + +static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = { + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x69), + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f), + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b), + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02), +}; + struct qmp_ufs_offsets { u16 serdes; u16 pcs; @@ -703,6 +765,10 @@ static const char * const sm8450_ufs_phy_clk_l[] = { "qref", "ref", "ref_aux", }; +static const char * const sm8550_ufs_phy_clk_l[] = { + "qref", "ref", +}; + static const char * const sdm845_ufs_phy_clk_l[] = { "ref", "ref_aux", }; @@ -721,6 +787,15 @@ static const struct qmp_ufs_offsets qmp_ufs_offsets_v5 = { .rx2 = 0xa00, }; +static const struct qmp_ufs_offsets qmp_ufs_offsets_v6 = { + .serdes = 0, + .pcs = 0x400, + .tx = 0x1000, + .rx = 0x1200, + .tx2 = 0x1800, + .rx2 = 0x1a00, +}; + static const struct qmp_phy_cfg msm8996_ufsphy_cfg = { .lanes = 1, @@ -958,6 +1033,28 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg = { .regs = sm8150_ufsphy_regs_layout, }; +static const struct qmp_phy_cfg sm8550_ufsphy_cfg = { + .lanes = 2, + + .offsets = &qmp_ufs_offsets_v6, + + .tbls = { + .serdes = sm8550_ufsphy_serdes, + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_serdes), + .tx = sm8550_ufsphy_tx, + .tx_num = ARRAY_SIZE(sm8550_ufsphy_tx), + .rx = sm8550_ufsphy_rx, + .rx_num = ARRAY_SIZE(sm8550_ufsphy_rx), + .pcs = sm8550_ufsphy_pcs, + .pcs_num = ARRAY_SIZE(sm8550_ufsphy_pcs), + }, + .clk_list = sm8550_ufs_phy_clk_l, + .num_clks = ARRAY_SIZE(sm8550_ufs_phy_clk_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = sm8550_ufsphy_regs_layout, +}; + static void qmp_ufs_configure_lane(void __iomem *base, const struct qmp_phy_init_tbl tbl[], int num, @@ -1467,6 +1564,9 @@ static const struct of_device_id qmp_ufs_of_match_table[] = { }, { .compatible = "qcom,sm8450-qmp-ufs-phy", .data = &sm8450_ufsphy_cfg, + }, { + .compatible = "qcom,sm8550-qmp-ufs-phy", + .data = &sm8550_ufsphy_cfg, }, { }, }; -- 2.34.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v2 6/6] phy: qcom-qmp-ufs: Add SM8550 support 2023-01-12 13:05 ` [PATCH v2 6/6] phy: qcom-qmp-ufs: Add SM8550 support Abel Vesa @ 2023-01-12 15:29 ` Johan Hovold 2023-01-13 18:35 ` Vinod Koul 1 sibling, 0 replies; 11+ messages in thread From: Johan Hovold @ 2023-01-12 15:29 UTC (permalink / raw) To: Abel Vesa Cc: Andy Gross, Bjorn Andersson, Konrad Dybcio, vkoul@kernel.org, Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski, linux-arm-msm, linux-phy, devicetree, Linux Kernel Mailing List On Thu, Jan 12, 2023 at 03:05:42PM +0200, Abel Vesa wrote: > Add SM8550 specific register layout and table configs. > > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > --- > drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 100 ++++++++++++++++++++++++ > 1 file changed, 100 insertions(+) > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c > index 5936a3a05002..a9b666f32f59 100644 > --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c > @@ -95,6 +95,13 @@ static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { > [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL, > }; > > +static const char * const sm8550_ufs_phy_clk_l[] = { > + "qref", "ref", > +}; These clocks would to be added to the binding too, but based on: https://lore.kernel.org/r/20230112135926.1572191-1-abel.vesa@linaro.org you really don't need these at all and what you call 'qref' (GCC_UFS_PHY_PHY_AUX_CLK) is just 'ref_aux' below. > + > static const char * const sdm845_ufs_phy_clk_l[] = { > "ref", "ref_aux", > }; > @@ -721,6 +787,15 @@ static const struct qmp_ufs_offsets qmp_ufs_offsets_v5 = { > .rx2 = 0xa00, > }; > > +static const struct qmp_ufs_offsets qmp_ufs_offsets_v6 = { > + .serdes = 0, > + .pcs = 0x400, Zero pad .pcs to 4 digits? > + .tx = 0x1000, > + .rx = 0x1200, > + .tx2 = 0x1800, > + .rx2 = 0x1a00, > +}; Johan ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 6/6] phy: qcom-qmp-ufs: Add SM8550 support 2023-01-12 13:05 ` [PATCH v2 6/6] phy: qcom-qmp-ufs: Add SM8550 support Abel Vesa 2023-01-12 15:29 ` Johan Hovold @ 2023-01-13 18:35 ` Vinod Koul 2023-01-16 14:14 ` Abel Vesa 1 sibling, 1 reply; 11+ messages in thread From: Vinod Koul @ 2023-01-13 18:35 UTC (permalink / raw) To: Abel Vesa, mani Cc: Andy Gross, Bjorn Andersson, Konrad Dybcio, Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski, linux-arm-msm, linux-phy, devicetree, Linux Kernel Mailing List On 12-01-23, 15:05, Abel Vesa wrote: > Add SM8550 specific register layout and table configs. Not related, but was this tested with the UFS Gear 4 support from Mani? It would be great to have that added (here or separately) > > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > --- > drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 100 ++++++++++++++++++++++++ > 1 file changed, 100 insertions(+) > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c > index 5936a3a05002..a9b666f32f59 100644 > --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c > @@ -95,6 +95,13 @@ static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { > [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL, > }; > > +static const unsigned int sm8550_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { > + [QPHY_START_CTRL] = QPHY_V6_PCS_UFS_PHY_START, > + [QPHY_PCS_READY_STATUS] = QPHY_V6_PCS_UFS_READY_STATUS, > + [QPHY_SW_RESET] = QPHY_V6_PCS_UFS_SW_RESET, > + [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_UFS_POWER_DOWN_CONTROL, > +}; > + > static const struct qmp_phy_init_tbl msm8996_ufsphy_serdes[] = { > QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), > QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7), > @@ -599,6 +606,61 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_pcs[] = { > QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a), > }; > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = { > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07), > +}; > + > +static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = { > + QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x05), > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07), > +}; > + > +static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = { > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c), > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4, 0x0f), > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e), > + > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2), > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xc2), > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3, 0x1a), > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6, 0x60), > + > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B3, 0x9e), > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B6, 0x60), > + > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B3, 0x9e), > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B4, 0x0e), > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B5, 0x36), > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02), > +}; > + > +static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = { > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x69), > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f), > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b), > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02), > +}; > + > struct qmp_ufs_offsets { > u16 serdes; > u16 pcs; > @@ -703,6 +765,10 @@ static const char * const sm8450_ufs_phy_clk_l[] = { > "qref", "ref", "ref_aux", > }; > > +static const char * const sm8550_ufs_phy_clk_l[] = { > + "qref", "ref", > +}; > + > static const char * const sdm845_ufs_phy_clk_l[] = { > "ref", "ref_aux", > }; > @@ -721,6 +787,15 @@ static const struct qmp_ufs_offsets qmp_ufs_offsets_v5 = { > .rx2 = 0xa00, > }; > > +static const struct qmp_ufs_offsets qmp_ufs_offsets_v6 = { > + .serdes = 0, > + .pcs = 0x400, > + .tx = 0x1000, > + .rx = 0x1200, > + .tx2 = 0x1800, > + .rx2 = 0x1a00, > +}; > + > static const struct qmp_phy_cfg msm8996_ufsphy_cfg = { > .lanes = 1, > > @@ -958,6 +1033,28 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg = { > .regs = sm8150_ufsphy_regs_layout, > }; > > +static const struct qmp_phy_cfg sm8550_ufsphy_cfg = { > + .lanes = 2, > + > + .offsets = &qmp_ufs_offsets_v6, > + > + .tbls = { > + .serdes = sm8550_ufsphy_serdes, > + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_serdes), > + .tx = sm8550_ufsphy_tx, > + .tx_num = ARRAY_SIZE(sm8550_ufsphy_tx), > + .rx = sm8550_ufsphy_rx, > + .rx_num = ARRAY_SIZE(sm8550_ufsphy_rx), > + .pcs = sm8550_ufsphy_pcs, > + .pcs_num = ARRAY_SIZE(sm8550_ufsphy_pcs), > + }, > + .clk_list = sm8550_ufs_phy_clk_l, > + .num_clks = ARRAY_SIZE(sm8550_ufs_phy_clk_l), > + .vreg_list = qmp_phy_vreg_l, > + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), > + .regs = sm8550_ufsphy_regs_layout, > +}; > + > static void qmp_ufs_configure_lane(void __iomem *base, > const struct qmp_phy_init_tbl tbl[], > int num, > @@ -1467,6 +1564,9 @@ static const struct of_device_id qmp_ufs_of_match_table[] = { > }, { > .compatible = "qcom,sm8450-qmp-ufs-phy", > .data = &sm8450_ufsphy_cfg, > + }, { > + .compatible = "qcom,sm8550-qmp-ufs-phy", > + .data = &sm8550_ufsphy_cfg, > }, > { }, > }; > -- > 2.34.1 -- ~Vinod ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 6/6] phy: qcom-qmp-ufs: Add SM8550 support 2023-01-13 18:35 ` Vinod Koul @ 2023-01-16 14:14 ` Abel Vesa 0 siblings, 0 replies; 11+ messages in thread From: Abel Vesa @ 2023-01-16 14:14 UTC (permalink / raw) To: Vinod Koul Cc: mani, Andy Gross, Bjorn Andersson, Konrad Dybcio, Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski, linux-arm-msm, linux-phy, devicetree, Linux Kernel Mailing List On 23-01-14 00:05:16, Vinod Koul wrote: > On 12-01-23, 15:05, Abel Vesa wrote: > > Add SM8550 specific register layout and table configs. > > Not related, but was this tested with the UFS Gear 4 support from Mani? > It would be great to have that added (here or separately) I mentioned both Mani's and Dmitry's patchsets in the cover letter. This patchset is based on both those patchsets. > > > > > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > > --- > > drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 100 ++++++++++++++++++++++++ > > 1 file changed, 100 insertions(+) > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c > > index 5936a3a05002..a9b666f32f59 100644 > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c > > @@ -95,6 +95,13 @@ static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { > > [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL, > > }; > > > > +static const unsigned int sm8550_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { > > + [QPHY_START_CTRL] = QPHY_V6_PCS_UFS_PHY_START, > > + [QPHY_PCS_READY_STATUS] = QPHY_V6_PCS_UFS_READY_STATUS, > > + [QPHY_SW_RESET] = QPHY_V6_PCS_UFS_SW_RESET, > > + [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_UFS_POWER_DOWN_CONTROL, > > +}; > > + > > static const struct qmp_phy_init_tbl msm8996_ufsphy_serdes[] = { > > QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), > > QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7), > > @@ -599,6 +606,61 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_pcs[] = { > > QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a), > > }; > > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = { > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9), > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11), > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01), > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04), > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00), > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a), > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18), > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14), > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f), > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06), > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c), > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a), > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18), > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14), > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99), > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07), > > +}; > > + > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = { > > + QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x05), > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07), > > +}; > > + > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = { > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c), > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4, 0x0f), > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e), > > + > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2), > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xc2), > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3, 0x1a), > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6, 0x60), > > + > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B3, 0x9e), > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B6, 0x60), > > + > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B3, 0x9e), > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B4, 0x0e), > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B5, 0x36), > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02), > > +}; > > + > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = { > > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x69), > > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f), > > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), > > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b), > > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02), > > +}; > > + > > struct qmp_ufs_offsets { > > u16 serdes; > > u16 pcs; > > @@ -703,6 +765,10 @@ static const char * const sm8450_ufs_phy_clk_l[] = { > > "qref", "ref", "ref_aux", > > }; > > > > +static const char * const sm8550_ufs_phy_clk_l[] = { > > + "qref", "ref", > > +}; > > + > > static const char * const sdm845_ufs_phy_clk_l[] = { > > "ref", "ref_aux", > > }; > > @@ -721,6 +787,15 @@ static const struct qmp_ufs_offsets qmp_ufs_offsets_v5 = { > > .rx2 = 0xa00, > > }; > > > > +static const struct qmp_ufs_offsets qmp_ufs_offsets_v6 = { > > + .serdes = 0, > > + .pcs = 0x400, > > + .tx = 0x1000, > > + .rx = 0x1200, > > + .tx2 = 0x1800, > > + .rx2 = 0x1a00, > > +}; > > + > > static const struct qmp_phy_cfg msm8996_ufsphy_cfg = { > > .lanes = 1, > > > > @@ -958,6 +1033,28 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg = { > > .regs = sm8150_ufsphy_regs_layout, > > }; > > > > +static const struct qmp_phy_cfg sm8550_ufsphy_cfg = { > > + .lanes = 2, > > + > > + .offsets = &qmp_ufs_offsets_v6, > > + > > + .tbls = { > > + .serdes = sm8550_ufsphy_serdes, > > + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_serdes), > > + .tx = sm8550_ufsphy_tx, > > + .tx_num = ARRAY_SIZE(sm8550_ufsphy_tx), > > + .rx = sm8550_ufsphy_rx, > > + .rx_num = ARRAY_SIZE(sm8550_ufsphy_rx), > > + .pcs = sm8550_ufsphy_pcs, > > + .pcs_num = ARRAY_SIZE(sm8550_ufsphy_pcs), > > + }, > > + .clk_list = sm8550_ufs_phy_clk_l, > > + .num_clks = ARRAY_SIZE(sm8550_ufs_phy_clk_l), > > + .vreg_list = qmp_phy_vreg_l, > > + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), > > + .regs = sm8550_ufsphy_regs_layout, > > +}; > > + > > static void qmp_ufs_configure_lane(void __iomem *base, > > const struct qmp_phy_init_tbl tbl[], > > int num, > > @@ -1467,6 +1564,9 @@ static const struct of_device_id qmp_ufs_of_match_table[] = { > > }, { > > .compatible = "qcom,sm8450-qmp-ufs-phy", > > .data = &sm8450_ufsphy_cfg, > > + }, { > > + .compatible = "qcom,sm8550-qmp-ufs-phy", > > + .data = &sm8550_ufsphy_cfg, > > }, > > { }, > > }; > > -- > > 2.34.1 > > -- > ~Vinod ^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2023-01-16 14:34 UTC | newest] Thread overview: 11+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-01-12 13:05 [PATCH v2 0/6] phy: qualcomm: Add UFS support for SM8550 Abel Vesa 2023-01-12 13:05 ` [PATCH v2 1/6] dt-bindings: phy: Add QMP UFS PHY comptible " Abel Vesa 2023-01-12 14:32 ` Krzysztof Kozlowski 2023-01-12 13:05 ` [PATCH v2 2/6] phy: qcom-qmp: qserdes-com: Add v6 register offsets Abel Vesa 2023-01-12 13:05 ` [PATCH v2 3/6] phy: qcom-qmp: qserdes-txrx: " Abel Vesa 2023-01-12 13:05 ` [PATCH v2 4/6] phy: qcom-qmp: qserdes-txrx-ufs: " Abel Vesa 2023-01-12 13:05 ` [PATCH v2 5/6] phy: qcom-qmp: pcs-ufs: " Abel Vesa 2023-01-12 13:05 ` [PATCH v2 6/6] phy: qcom-qmp-ufs: Add SM8550 support Abel Vesa 2023-01-12 15:29 ` Johan Hovold 2023-01-13 18:35 ` Vinod Koul 2023-01-16 14:14 ` Abel Vesa
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