From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C69FC46467 for ; Thu, 19 Jan 2023 12:09:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230462AbjASMJw (ORCPT ); Thu, 19 Jan 2023 07:09:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40386 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230412AbjASMJt (ORCPT ); Thu, 19 Jan 2023 07:09:49 -0500 Received: from mail-wr1-x42d.google.com (mail-wr1-x42d.google.com [IPv6:2a00:1450:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D09434B885 for ; Thu, 19 Jan 2023 04:09:46 -0800 (PST) Received: by mail-wr1-x42d.google.com with SMTP id b5so1693158wrn.0 for ; Thu, 19 Jan 2023 04:09:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=iJM/h+lldPXDlTcAuDUdunbYkmcG7VHMb5074kf6tA0=; b=P1XDghb5jL3e1MRSpcUCp94PDNobl2vr2DOi5acBorxHYFvq6rY8KEpa/V6WNDlFSN ai8t3W95n5hWIn/P6vOafgpSvOgDRbsNcGX1RbE/vHw5iGSYs/3aQyYdPe/tG/jS0n1v HqLo582UeEhdXlcVT3jRHVfQkgDO5Yc9pZJPfPRpV26F10Xo6t5WYWQONLSixF9YOt5w 0a/9INrTDeYQHUa+Z7p7NQoAS5Y1lmB5MVJa16LK+DJHmp7wjNgVWhCGgwK4AqXmFx24 YV8ZptHfnkPtIqS50zj/mBP5ZSiq1Uec1u6XNKrpwiSt5fw467Jb5q3WuT3a+qN78hKX 2HqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=iJM/h+lldPXDlTcAuDUdunbYkmcG7VHMb5074kf6tA0=; b=JZrk/YP0oxRZTJJ33Bi/UaLetOq8gMb4tDkMxKTpxkU4tn2qzY+tmxa1yMOXJnhiEV blLU4WsDpqNnyVcjj74DHIezc/B7DdpKLlCuTbierSafCmLd3GnTpCHRpfkjI9x4acN8 JBuCNBWTGxsPE6mSTCoxZq5OmsMgVimV1SS5GiuEuASr8xe5ggUTuocPid/i2InyaO1d 8zY40wqVQXwBj0roXJcrVvSiAlSFJTjfbXq9gLhNMJ4fXdqsrbyQHyC2JQntxsNZI6Vz xe4ULCkQFN6RpcCsiBkqhZZwA6kkS3jprKBJndEW9UzmG2mgpmgbPww7OyLSszDtAMkd Wspw== X-Gm-Message-State: AFqh2koYRn2sDat6HNQ4zhhFpNiqP/Jkg1k+0i94uPcDo6/8G9jqPxOO 5LWgU+jZiDtepgaugYbe+ebhMg== X-Google-Smtp-Source: AMrXdXs7QQi4g4VYJPo232c8Q5V9/773sn0KHvyX6ENIS2uuYmJA9wUi1iKQcFkDf4ozmhlPdvZszw== X-Received: by 2002:a5d:6b09:0:b0:2be:110d:5d59 with SMTP id v9-20020a5d6b09000000b002be110d5d59mr8620305wrw.51.1674130185366; Thu, 19 Jan 2023 04:09:45 -0800 (PST) Received: from linaro.org ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id f2-20020adfdb42000000b0024274a5db0asm33607850wrj.2.2023.01.19.04.09.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Jan 2023 04:09:44 -0800 (PST) Date: Thu, 19 Jan 2023 14:09:43 +0200 From: Abel Vesa To: Johan Hovold Cc: Bjorn Andersson , Rob Herring , Konrad Dybcio , Andy Gross , Krzysztof Kozlowski , devicetree@vger.kernel.org, Linux Kernel Mailing List , linux-arm-msm@vger.kernel.org Subject: Re: [PATCH v2 0/2] arm64: dts: qcom: sm8550: Add PCIe HC and PHY support Message-ID: References: <20230118230526.1499328-1-abel.vesa@linaro.org> <167408614065.2989059.2950818972854332656.b4-ty@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 23-01-19 08:33:20, Johan Hovold wrote: > On Wed, Jan 18, 2023 at 05:55:31PM -0600, Bjorn Andersson wrote: > > On Thu, 19 Jan 2023 01:05:24 +0200, Abel Vesa wrote: > > > This patchset adds PCIe controllers and PHYs support to SM8550 platform > > > and enables them on the MTP board. > > > > > > The v1 was here: > > > https://lore.kernel.org/all/20221116130430.2812173-1-abel.vesa@linaro.org/ > > > > > > Changes since v1: > > > * ordered pcie related nodes alphabetically in MTP dts > > > * dropped the pipe_mux, phy_pipe and ref clocks from the pcie nodes > > > * dropped the child node from the phy nodes, like Johan suggested, > > > and updated to use the sc8280xp binding scheme > > > * changed "pcie_1_nocsr_com_phy_reset" 2nd reset name of pcie1_phy > > > to "nocsr" > > > * reordered all pcie nodes properties to look similar to the ones > > > from sc8280xp > > > > > > [...] > > > > Applied, thanks! > > > > [1/2] arm64: dts: qcom: sm8550: Add PCIe PHYs and controllers nodes > > commit: 7d1158c984d37e79ab8bb55ab152a0b35566cb89 > > [2/2] arm64: dts: qcom: sm8550-mtp: Add PCIe PHYs and controllers nodes > > commit: 1eeef306b5d80494cdb149f058013c3ab43984b4 > > I believe there were still some changes needed to the controller > and PHY bindings so this should not have been merged. > > https://lore.kernel.org/all/Y8fuUI4xaNkADkWl@hovoldconsulting.com/ > https://lore.kernel.org/lkml/Y8giHJMtPu4wTlmA@hovoldconsulting.com/ > > Perhaps in the future you can send the dts changes along with the (PHY) > driver changes so that they can be kept in lock-step and avoid this. Well, that is a bit hard to do, because phy patches are based on linux-phy/next, while dtsi patches are based on Bjorn's tree which, so ... > > Johan