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[73.214.169.22]) by smtp.gmail.com with ESMTPSA id w193-20020a022aca000000b003a5de29178esm371182jaw.104.2023.02.02.16.15.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Feb 2023 16:15:08 -0800 (PST) Date: Thu, 2 Feb 2023 19:15:07 -0500 From: Brian Masney To: Konrad Dybcio Cc: Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [RFT PATCH 05/14] arm64: dts: qcom: sc8280xp: correct TLMM gpio-ranges Message-ID: References: <20230201155105.282708-1-krzysztof.kozlowski@linaro.org> <20230201155105.282708-6-krzysztof.kozlowski@linaro.org> <25f5a750-b51c-7d7b-0d50-5b2f78de8512@linaro.org> <1319a973-26ae-8c11-d967-8720aaf894df@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1319a973-26ae-8c11-d967-8720aaf894df@linaro.org> User-Agent: Mutt/2.2.7 (2022-08-07) Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Fri, Feb 03, 2023 at 01:05:35AM +0100, Konrad Dybcio wrote: > On 3.02.2023 00:59, Brian Masney wrote: > > For others quick reference, Konrad is talking about this line from > > sa8540p-ride.dts: > > > > reset-gpios = <&tlmm 228 GPIO_ACTIVE_LOW>; > > > > I noticed that earlier but assumed this was one based. However, looking > > at pinctrl-sc8280xp.c I see gpio0..gpio227 defined. > > + gpio229 is the reset pin for the UFS card slot We don't have the UFS card slot on the sa8540p exposed. However, it is available on the sa8295p. The original DTS in upstream listed 230 pins, however pinctrl-sc8280xp.c lists 233 pins and the two UFS pins match what we have in DTS. static const struct pinctrl_pin_desc sc8280xp_pins[] = { PINCTRL_PIN(0, "GPIO_0"), ... PINCTRL_PIN(227, "GPIO_227"), PINCTRL_PIN(228, "UFS_RESET"), PINCTRL_PIN(229, "UFS1_RESET"), PINCTRL_PIN(230, "SDC2_CLK"), PINCTRL_PIN(231, "SDC2_CMD"), PINCTRL_PIN(232, "SDC2_DATA"), Rescind-Reviewed-by: Brian Masney