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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id q18sm1183378ood.35.2021.01.14.09.57.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jan 2021 09:57:28 -0800 (PST) Date: Thu, 14 Jan 2021 11:57:26 -0600 From: Bjorn Andersson To: AngeloGioacchino Del Regno Cc: agross@kernel.org, linux-kernel@vger.kernel.org, konrad.dybcio@somainline.org, marijn.suijten@somainline.org, martin.botka@somainline.org, robh+dt@kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-i2c@vger.kernel.org, phone-devel@vger.kernel.org Subject: Re: [PATCH v2 2/3] i2c: qup: Introduce SCL/SDA noise rejection Message-ID: References: <20210114174909.399284-1-angelogioacchino.delregno@somainline.org> <20210114174909.399284-3-angelogioacchino.delregno@somainline.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210114174909.399284-3-angelogioacchino.delregno@somainline.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Thu 14 Jan 11:49 CST 2021, AngeloGioacchino Del Regno wrote: > Some I2C devices may be glitchy due to electrical noise coming > from the device itself or because of possible board design issues. > To overcome this issue, the QUP's I2C in Qualcomm SoCs supports > a noise rejection setting for both SCL and SDA lines. > > Introduce a setting for noise rejection through device properties, > "qcom,noise-reject-sda" and "qcom,noise-reject-scl", which will > be used to set the level of noise rejection sensitivity. > If the properties are not specified, noise rejection will not be > enabled. > This looks reasonable, just some small nits below. > Signed-off-by: AngeloGioacchino Del Regno > --- > drivers/i2c/busses/i2c-qup.c | 17 +++++++++++++++++ > 1 file changed, 17 insertions(+) > > diff --git a/drivers/i2c/busses/i2c-qup.c b/drivers/i2c/busses/i2c-qup.c > index 5a47915869ae..af51234a60ba 100644 > --- a/drivers/i2c/busses/i2c-qup.c > +++ b/drivers/i2c/busses/i2c-qup.c > @@ -8,6 +8,7 @@ > #include > #include > #include > +#include If you move this one step up you'll maintain the sort order. > #include > #include > #include > @@ -39,6 +40,8 @@ > #define QUP_MX_READ_CNT 0x208 > #define QUP_IN_FIFO_BASE 0x218 > #define QUP_I2C_CLK_CTL 0x400 > +#define QUP_I2C_CLK_CTL_SDA_NR GENMASK(27, 26) > +#define QUP_I2C_CLK_CTL_SCL_NR GENMASK(25, 24) > #define QUP_I2C_STATUS 0x404 > #define QUP_I2C_MASTER_GEN 0x408 > > @@ -1663,6 +1666,7 @@ static int qup_i2c_probe(struct platform_device *pdev) > int ret, fs_div, hs_div; > u32 src_clk_freq = DEFAULT_SRC_CLK; > u32 clk_freq = DEFAULT_CLK_FREQ; > + u32 noise_reject_scl = 0, noise_reject_sda = 0; You shouldn't need to initialize these, device_property_read_u32() won't return 0 without updating them. > int blocks; > bool is_qup_v1; > > @@ -1860,6 +1864,19 @@ static int qup_i2c_probe(struct platform_device *pdev) > qup->clk_ctl = ((fs_div / 2) << 16) | (hs_div << 8) | (fs_div & 0xff); > } > > + /* SCL/SDA Noise rejection (optional) */ > + ret = device_property_read_u32(qup->dev, "qcom,noise-reject-scl", > + &noise_reject_scl); > + if (ret == 0) > + qup->clk_ctl |= FIELD_PREP(QUP_I2C_CLK_CTL_SCL_NR, > + noise_reject_scl); I would prefer if you didn't break this line. > + > + ret = device_property_read_u32(qup->dev, "qcom,noise-reject-sda", > + &noise_reject_sda); > + if (ret == 0) > + qup->clk_ctl |= FIELD_PREP(QUP_I2C_CLK_CTL_SDA_NR, > + noise_reject_sda); Ditto. Regards, Bjorn > + > /* > * Time it takes for a byte to be clocked out on the bus. > * Each byte takes 9 clock cycles (8 bits + 1 ack). > -- > 2.29.2 >