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[35.233.69.230]) by smtp.gmail.com with ESMTPSA id v204sm3995339wmg.38.2021.02.17.09.24.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 09:24:35 -0800 (PST) Date: Wed, 17 Feb 2021 17:24:32 +0000 From: Quentin Perret To: Mate Toth-Pal , r@google.com Cc: Catalin Marinas , Will Deacon , Marc Zyngier , James Morse , Julien Thierry , Suzuki K Poulose , Rob Herring , Frank Rowand , devicetree@vger.kernel.org, android-kvm@google.com, linux-kernel@vger.kernel.org, kernel-team@android.com, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, Fuad Tabba , Mark Rutland , David Brazdil , nd@arm.com Subject: Re: [RFC PATCH v2 00/26] KVM/arm64: A stage 2 for the host Message-ID: References: <20210108121524.656872-1-qperret@google.com> <18756e24-ca87-9c98-0e20-7c7a4c4d5433@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <18756e24-ca87-9c98-0e20-7c7a4c4d5433@arm.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Mate, On Wednesday 17 Feb 2021 at 17:27:07 (+0100), Mate Toth-Pal wrote: > We tested the pKVM changes pulled from here: > > > > https://android-kvm.googlesource.com/linux qperret/host-stage2-v2 > > > We were using a target with Arm architecture with FEAT_S2FWB, and found that > there is a bug in the patch. > > > It turned out that the Kernel checks for the extension, and sets up the > stage 2 translation so that it forces the host memory type to write-through. > However it seems that the code doesn't turn on the feature in the HCR_EL2 > register. > > > We were able to fix the issue by applying the following patch: > > > diff --git a/arch/arm64/kvm/hyp/nvhe/mem_protect.c > b/arch/arm64/kvm/hyp/nvhe/mem_protect.c > index 0cd3eb178f3b..e8521a072ea6 100644 > --- a/arch/arm64/kvm/hyp/nvhe/mem_protect.c > +++ b/arch/arm64/kvm/hyp/nvhe/mem_protect.c > @@ -105,6 +105,8 @@ int kvm_host_prepare_stage2(void *mem_pgt_pool, void > *dev_pgt_pool) >                 params->vttbr = kvm_get_vttbr(mmu); >                 params->vtcr = host_kvm.arch.vtcr; >                 params->hcr_el2 |= HCR_VM; > +               if (cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) > +                       params->hcr_el2 |= HCR_FWB; >                 __flush_dcache_area(params, sizeof(*params)); >         } Aha, indeed, this looks right. I'll double check HCR_EL2 to see if I'm missing any other, and I'll add this to v3. Thanks for testing, and the for the report. Quentin