From: Matthias Kaehlcke <mka@chromium.org>
To: Sandeep Maheswaram <sanm@codeaurora.org>
Cc: Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Kishon Vijay Abraham I <kishon@ti.com>,
Rob Herring <robh+dt@kernel.org>, Vinod Koul <vkoul@kernel.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Wesley Cheng <wcheng@codeaurora.org>,
Stephen Boyd <swboyd@chromium.org>,
Doug Anderson <dianders@chromium.org>,
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-phy@lists.infradead.org,
linux-usb@vger.kernel.org, Manu Gautam <mgautam@codeaurora.org>
Subject: Re: [PATCH 3/3] arm64: dts: qcom: sc7280: Add USB related nodes
Date: Thu, 18 Mar 2021 12:03:10 -0700 [thread overview]
Message-ID: <YFOj7lrOHZE1q2If@google.com> (raw)
In-Reply-To: <1615978901-4202-4-git-send-email-sanm@codeaurora.org>
On Wed, Mar 17, 2021 at 04:31:41PM +0530, Sandeep Maheswaram wrote:
> Add nodes for DWC3 USB controller, QMP and HS USB PHYs.
>
> Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
> ---
> arch/arm64/boot/dts/qcom/sc7280-idp.dts | 39 +++++++++
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 149 ++++++++++++++++++++++++++++++++
> 2 files changed, 188 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> index 54d2cb3..251a5b5 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> @@ -257,3 +257,42 @@
> bias-pull-up;
> };
> };
> +
> +&usb_1 {
> + status = "okay";
> +};
> +
> +&usb_1_dwc3 {
> + dr_mode = "host";
> +};
> +
> +&usb_1_hsphy {
> + status = "okay";
> +
> + vdda-pll-supply = <&vreg_l10c_0p8>;
> + vdda33-supply = <&vreg_l2b_3p0>;
> + vdda18-supply = <&vreg_l1c_1p8>;
> +};
> +
> +&usb_1_qmpphy {
> + status = "okay";
> +
> + vdda-phy-supply = <&vreg_l6b_1p2>;
> + vdda-pll-supply = <&vreg_l1b_0p8>;
> +};
> +
> +&usb_2 {
> + status = "okay";
> +};
> +
> +&usb_2_dwc3 {
> + dr_mode = "peripheral";
> +};
> +
> +&usb_2_hsphy {
> + status = "okay";
> +
> + vdda-pll-supply = <&vreg_l10c_0p8>;
> + vdda33-supply = <&vreg_l2b_3p0>;
> + vdda18-supply = <&vreg_l1c_1p8>;
> +};
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 39cf0be..a785f65 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -305,6 +305,155 @@
> };
> };
>
> + usb_1_hsphy: phy@88e3000 {
> + compatible = "qcom,sc7280-usb-hs-phy",
> + "qcom,usb-snps-hs-7nm-phy";
> + reg = <0 0x088e3000 0 0x400>;
> + status = "disabled";
> + #phy-cells = <0>;
> +
> + clocks = <&rpmhcc RPMH_CXO_CLK>;
> + clock-names = "ref";
> +
> + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
> + };
> +
> + usb_2_hsphy: phy@88e4000 {
> + compatible = "qcom,sc7280-usb-hs-phy",
> + "qcom,usb-snps-hs-7nm-phy";
> + reg = <0 0x088e4000 0 0x400>;
> + status = "disabled";
> + #phy-cells = <0>;
> +
> + clocks = <&rpmhcc RPMH_CXO_CLK>;
> + clock-names = "ref";
> +
> + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
> + };
> +
> + usb_1_qmpphy: phy@88e9000 {
> + compatible = "qcom,sm8250-qmp-usb3-phy";
> + reg = <0 0x088e9000 0 0x200>,
> + <0 0x088e8000 0 0x20>;
> + reg-names = "reg-base", "dp_com";
> + status = "disabled";
> + #clock-cells = <1>;
IIUC this means that the PHY is a clock provider. Which clocks does it
provide? How would a possible consumer specify the clock it wants to
use? I couldn't find the corresponding definitions in the header of the
binding
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>,
> + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
> + clock-names = "aux", "ref_clk_src", "com_aux";
> +
> + resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
> + <&gcc GCC_USB3_PHY_PRIM_BCR>;
> + reset-names = "phy", "common";
> +
> + usb_1_ssphy: lanes@88e9200 {
> + reg = <0 0x088e9200 0 0x200>,
> + <0 0x088e9400 0 0x200>,
> + <0 0x088e9c00 0 0x400>,
> + <0 0x088e9600 0 0x200>,
> + <0 0x088e9800 0 0x200>,
> + <0 0x088e9a00 0 0x100>;
> + #phy-cells = <0>;
> + clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
> + clock-names = "pipe0";
> + clock-output-names = "usb3_phy_pipe_clk_src";
> + };
> + };
> +
> + usb_2: usb@8cf8800 {
> + compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
> + reg = <0 0x08cf8800 0 0x400>;
> + status = "disabled";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + dma-ranges;
> +
> + clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
> + <&gcc GCC_USB30_SEC_MASTER_CLK>,
> + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
> + <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
> + <&gcc GCC_USB30_SEC_SLEEP_CLK>;
> + clock-names = "cfg_noc", "core", "iface","mock_utmi",
> + "sleep";
> +
> + assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
> + <&gcc GCC_USB30_SEC_MASTER_CLK>;
> + assigned-clock-rates = <19200000>, <200000000>;
> +
> + interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
> + <&pdc 13 IRQ_TYPE_EDGE_RISING>,
> + <&pdc 12 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "hs_phy_irq",
> + "dm_hs_phy_irq", "dp_hs_phy_irq";
> +
> + power-domains = <&gcc GCC_USB30_SEC_GDSC>;
> +
> + resets = <&gcc GCC_USB30_SEC_BCR>;
> +
> + usb_2_dwc3: dwc3@8c00000 {
> + compatible = "snps,dwc3";
> + reg = <0 0x08c00000 0 0xe000>;
> + interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
> + iommus = <&apps_smmu 0xa0 0x0>;
> + snps,dis_u2_susphy_quirk;
> + snps,dis_enblslpm_quirk;
> + phys = <&usb_2_hsphy>;
> + phy-names = "usb2-phy";
> + maximum-speed = "high-speed";
> + };
> + };
> +
> + usb_1: usb@a6f8800 {
> + compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
> + reg = <0 0x0a6f8800 0 0x400>;
> + status = "disabled";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + dma-ranges;
> +
> + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
> + <&gcc GCC_USB30_PRIM_MASTER_CLK>,
> + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
> + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
> + <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
> +
> + clock-names = "cfg_noc", "core", "iface", "mock_utmi",
> + "sleep";
> +
> + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
> + <&gcc GCC_USB30_PRIM_MASTER_CLK>;
> + assigned-clock-rates = <19200000>, <200000000>;
> +
> + interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
> + <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
> + <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
> + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
> + "dm_hs_phy_irq", "ss_phy_irq";
> +
> + power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
> +
> + resets = <&gcc GCC_USB30_PRIM_BCR>;
> +
> + usb_1_dwc3: dwc3@a600000 {
> + compatible = "snps,dwc3";
> + reg = <0 0x0a600000 0 0xe000>;
> + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
> + iommus = <&apps_smmu 0xe0 0x0>;
> + snps,dis_u2_susphy_quirk;
> + snps,dis_enblslpm_quirk;
> + phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
> + phy-names = "usb2-phy", "usb3-phy";
The 'maximum-speed' isn't specified in difference to the other controller.
According to commit d3d245aee0b1 ("arm64: dts: qcom: sc7180: Add
maximum speed property for DWC3 USB node") the max speed is used to
configure the interconnect bandwidth. dwc3_qcom_interconnect_init() falls
back to super speed if the max speed is unknown, so it should be fine to
omit it, unless it is needed for something else.
prev parent reply other threads:[~2021-03-18 19:04 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-17 11:01 [PATCH 0/3] Add DT bindings and DT nodes for USB in SC7280 Sandeep Maheswaram
2021-03-17 11:01 ` [PATCH 1/3] dt-bindings: usb: qcom,dwc3: Add bindings for SC7280 Sandeep Maheswaram
2021-03-17 19:34 ` Matthias Kaehlcke
2021-03-23 21:01 ` Stephen Boyd
2021-03-26 0:22 ` Rob Herring
2021-03-17 11:01 ` [PATCH 2/3] dt-bindings: phy: qcom,usb-snps-femto-v2: " Sandeep Maheswaram
2021-03-17 20:03 ` Matthias Kaehlcke
2021-03-23 21:02 ` Stephen Boyd
2021-03-25 7:22 ` Vinod Koul
2021-03-17 11:01 ` [PATCH 3/3] arm64: dts: qcom: sc7280: Add USB related nodes Sandeep Maheswaram
2021-03-18 19:03 ` Matthias Kaehlcke [this message]
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