From: Stephan Gerhold <stephan@gerhold.net>
To: Leo Yan <leo.yan@linaro.org>
Cc: Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
Coresight ML <coresight@lists.linaro.org>,
Georgi Djakov <georgi.djakov@linaro.org>
Subject: Re: [PATCH] arm64: dts: msm8916: Enable CoreSight STM component
Date: Sat, 20 Mar 2021 16:35:20 +0100 [thread overview]
Message-ID: <YFYWOOdHT/qJk4Mr@gerhold.net> (raw)
In-Reply-To: <20210320025942.487916-1-leo.yan@linaro.org>
Hi Leo,
On Sat, Mar 20, 2021 at 10:59:42AM +0800, Leo Yan wrote:
> From: Georgi Djakov <georgi.djakov@linaro.org>
>
> Add DT binding for CoreSight System Trace Macrocell (STM) on msm8916,
> which can benefit the CoreSight development on DB410c.
>
> Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
> Signed-off-by: Leo Yan <leo.yan@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 1 +
> arch/arm64/boot/dts/qcom/msm8916.dtsi | 27 +++++++++++++++++++++++
> 2 files changed, 28 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
> index 3a9538e1ec97..dd87e5d739ab 100644
> --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
> +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
> @@ -406,6 +406,7 @@ &wcd_codec {
> &etm1 { status = "okay"; };
> &etm2 { status = "okay"; };
> &etm3 { status = "okay"; };
> +&stm { status = "okay"; };
> &etr { status = "okay"; };
> &funnel0 { status = "okay"; };
> &funnel1 { status = "okay"; };
This is alphabetically ordered so &stm should be on the line before &tpiu.
> diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
> index 402e891a84ab..892f1772e53c 100644
> --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
> [...]
> @@ -882,6 +889,26 @@ etm3_out: endpoint {
> };
> };
>
> + stm: stm@802000 {
And these nodes are sorted by their unit address (0x802000),
so stm@802000 should be the first coresight node, before cti@810000.
> + compatible = "arm,coresight-stm", "arm,primecell";
> + reg = <0x802000 0x1000>,
> + <0x9280000 0x180000>;
And please pad these addresses with zeroes so the order is more easily
visible, i.e.
+ reg = <0x00802000 0x1000>,
+ <0x09280000 0x180000>;
Thanks!
Stephan
next prev parent reply other threads:[~2021-03-20 15:42 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-20 2:59 [PATCH] arm64: dts: msm8916: Enable CoreSight STM component Leo Yan
2021-03-20 3:05 ` Leo Yan
2021-03-24 21:22 ` Mike Leach
2021-03-25 0:43 ` Leo Yan
2021-03-20 15:35 ` Stephan Gerhold [this message]
2021-03-21 12:21 ` Leo Yan
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