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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id w2sm4196653oov.23.2021.03.29.20.23.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Mar 2021 20:23:55 -0700 (PDT) Date: Mon, 29 Mar 2021 22:23:53 -0500 From: Bjorn Andersson To: Eric Anholt Cc: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Rob Clark , Sean Paul , Jordan Crouse , Robin Murphy , Will Deacon , Rob Herring , Joerg Roedel , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/2] arm64: dts: msm8996: Mark the GPU's SMMU as an adreno one. Message-ID: References: <20210326231303.3071950-1-eric@anholt.net> <20210326231303.3071950-2-eric@anholt.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210326231303.3071950-2-eric@anholt.net> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Fri 26 Mar 18:13 CDT 2021, Eric Anholt wrote: > This enables the adreno-specific SMMU path that sets HUPCF so > (user-managed) page faults don't wedge the GPU. > > Signed-off-by: Eric Anholt Acked-by: Bjorn Andersson @Will, can you pick this together with the driver patch? (So that they land in order) Regards, Bjorn > --- > > We've been seeing a flaky test per day or so in Mesa CI where the > kernel gets wedged after an iommu fault turns into CP errors. With > this patch, the CI isn't throwing the string of CP errors on the > faults in any of the ~10 jobs I've run so far. > > arch/arm64/boot/dts/qcom/msm8996.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi > index 6de136e3add9..432b87ec9c5e 100644 > --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi > @@ -1127,7 +1127,7 @@ cci_i2c1: i2c-bus@1 { > }; > > adreno_smmu: iommu@b40000 { > - compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; > + compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; > reg = <0x00b40000 0x10000>; > > #global-interrupts = <1>; > -- > 2.31.0 >