From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A03A7C433DB for ; Tue, 30 Mar 2021 03:42:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6571A60190 for ; Tue, 30 Mar 2021 03:42:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230122AbhC3Dl3 (ORCPT ); Mon, 29 Mar 2021 23:41:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46506 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229763AbhC3DlF (ORCPT ); Mon, 29 Mar 2021 23:41:05 -0400 Received: from mail-oo1-xc2d.google.com (mail-oo1-xc2d.google.com [IPv6:2607:f8b0:4864:20::c2d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 05BDBC061764 for ; Mon, 29 Mar 2021 20:41:04 -0700 (PDT) Received: by mail-oo1-xc2d.google.com with SMTP id j20-20020a4ad6d40000b02901b66fe8acd6so3459108oot.7 for ; Mon, 29 Mar 2021 20:41:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=R5DnXj5JMwGYgLeYbNNzgz0sybFWEJe/tT4bzed1uWw=; b=JZQqRbpd4dZ8jRSO7uxccTyXYklG+14Kb4jf+rvC8nOXnSkx1xIw05zeegfmUkbn65 vO1v5RKkqzmP4YxNpgGJEltv8FtAArebTr1dTnvpjReugBegj37uZHJlzUdMlAoFezxI RZQGrKZNCaTK+Nwo1+QG3I+WuCn+nGgQ3PPBTp2Pd0d/IENX0qVuRf4kzU+rY6pPpUqG cnJCyGM+rVswIpCEIBsL4l2zb3CX3WeLS3KTxDnd1zdq6ntZhflOzrVoYEobO62yLs0g QkhIFzekjvEKt0sb0zlcCatNk7z4La28eLIw6bES+EDYZsvCpMwcHOMmd7JXQK33vPGD z3eg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=R5DnXj5JMwGYgLeYbNNzgz0sybFWEJe/tT4bzed1uWw=; b=m67wxbZNzQsPTBPiitCvaT5RlxRTsHov9ISmCulqHdIG2zQtB8D/ATkOPCQpDgb8B/ CF/z2jTphbDMnq85SsW1ETLYN1VWfA5wSsnBVnHpoZg/MczSdXM8dBpTYVjw6pcBy4qL WZf5KXEgraf27GkLn3asyZ+zwZQkMee6qTHbMtqjFK33av/7Ee0W5wfubaSzB3sCz7e7 HVF5AFZ4qSTRP94CrDIizS8AzDt1DkLmuba7A/Ap0OIIdJTu7Jgz1jFRTroX9QRDRrEl pU4yc4OEd/Btfx1dnMrp12pqFO4aKwrRvJXWuRm+n+MslhW8NK6a62zXpZ7S4gcGM82u HJqg== X-Gm-Message-State: AOAM532QqdgDbx7E2wZmlKePWJTyod6z9FiRr1iRN8JtZflYxWvMzOOE OmzEl7sGwybjrfpMeU8rlmdmhg== X-Google-Smtp-Source: ABdhPJw2rOmcLo28VVQMtOuGXcfGwY870/kcdcwRU5b0o22efAkukGUJDHRjiiXJgfEK0i35yIKJvg== X-Received: by 2002:a4a:45d5:: with SMTP id y204mr23766808ooa.33.1617075664341; Mon, 29 Mar 2021 20:41:04 -0700 (PDT) Received: from builder.lan (104-57-184-186.lightspeed.austtx.sbcglobal.net. [104.57.184.186]) by smtp.gmail.com with ESMTPSA id 62sm3075739oto.60.2021.03.29.20.41.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Mar 2021 20:41:03 -0700 (PDT) Date: Mon, 29 Mar 2021 22:41:02 -0500 From: Bjorn Andersson To: Bartosz Dudziak Cc: Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , linux-clk@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH 3/5] arm: dts: qcom: Add support for MSM8226 SoC Message-ID: References: <20210326145816.9758-1-bartosz.dudziak@snejp.pl> <20210326145816.9758-4-bartosz.dudziak@snejp.pl> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210326145816.9758-4-bartosz.dudziak@snejp.pl> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Fri 26 Mar 09:58 CDT 2021, Bartosz Dudziak wrote: > This patch adds basic device tree support for MSM8226 SoC which belongs > to the Snapdragon 400 family. For now, this file adds the basic nodes > like gcc, pinctrl and other required configuration for booting up to > the serial console. > > Signed-off-by: Bartosz Dudziak > --- > arch/arm/boot/dts/qcom-msm8226.dtsi | 152 ++++++++++++++++++++++++++++ > 1 file changed, 152 insertions(+) > create mode 100644 arch/arm/boot/dts/qcom-msm8226.dtsi > > diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom-msm8226.dtsi > new file mode 100644 > index 0000000000..81bb19398e > --- /dev/null > +++ b/arch/arm/boot/dts/qcom-msm8226.dtsi > @@ -0,0 +1,152 @@ > +// SPDX-License-Identifier: GPL-2.0 Can you please make this BSD license? > +/* > + * Copyright (c) 2020, The Linux Foundation. All rights reserved. > + */ > + > +/dts-v1/; > + > +#include > +#include > + > +/ { > + #address-cells = <1>; > + #size-cells = <1>; > + model = "Qualcomm Technologies, Inc. MSM8226"; > + compatible = "qcom,msm8226"; model and compatible should always be specified in the .dts, so the ones specified here would be overwritten. So drop them here. > + interrupt-parent = <&intc>; > + > + chosen { }; > + > + memory { > + device_type = "memory"; > + /* We expect the bootloader to fill in the size */ > + reg = <0x0 0x0>; > + }; > + > + soc: soc { > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + compatible = "simple-bus"; > + > + intc: interrupt-controller@f9000000 { > + compatible = "qcom,msm-qgic2"; > + interrupt-controller; > + #interrupt-cells = <3>; > + reg = <0xF9000000 0x1000>, > + <0xF9002000 0x1000>; > + }; > + > + gcc: clock-controller@fc400000 { > + compatible = "qcom,gcc-msm8226"; > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; > + reg = <0xfc400000 0x4000>; > + }; > + > + msmgpio: pinctrl@fd510000 { Rename the label "tlmm" > + compatible = "qcom,msm8226-pinctrl"; > + reg = <0xfd510000 0x4000>; > + gpio-controller; > + #gpio-cells = <2>; > + gpio-ranges = <&msmgpio 0 0 117>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupts = ; > + }; > + > + blsp1_uart3: serial@f991f000 { > + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; > + reg = <0xf991f000 0x1000>; > + interrupts = ; > + clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; > + clock-names = "core", "iface"; > + status = "disabled"; > + }; > + > + restart@fc4ab000 { > + compatible = "qcom,pshold"; > + reg = <0xfc4ab000 0x4>; > + }; > + > + rng@f9bff000 { > + compatible = "qcom,prng"; > + reg = <0xf9bff000 0x200>; > + clocks = <&gcc GCC_PRNG_AHB_CLK>; > + clock-names = "core"; > + }; > + > + timer@f9020000 { > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + compatible = "arm,armv7-timer-mem"; It's nice to have compatible & reg first in the nodes. Regards, Bjorn > + reg = <0xf9020000 0x1000>; > + clock-frequency = <19200000>; > + > + frame@f9021000 { > + frame-number = <0>; > + interrupts = , > + ; > + reg = <0xf9021000 0x1000>, > + <0xf9022000 0x1000>; > + }; > + > + frame@f9023000 { > + frame-number = <1>; > + interrupts = ; > + reg = <0xf9023000 0x1000>; > + status = "disabled"; > + }; > + > + frame@f9024000 { > + frame-number = <2>; > + interrupts = ; > + reg = <0xf9024000 0x1000>; > + status = "disabled"; > + }; > + > + frame@f9025000 { > + frame-number = <3>; > + interrupts = ; > + reg = <0xf9025000 0x1000>; > + status = "disabled"; > + }; > + > + frame@f9026000 { > + frame-number = <4>; > + interrupts = ; > + reg = <0xf9026000 0x1000>; > + status = "disabled"; > + }; > + > + frame@f9027000 { > + frame-number = <5>; > + interrupts = ; > + reg = <0xf9027000 0x1000>; > + status = "disabled"; > + }; > + > + frame@f9028000 { > + frame-number = <6>; > + interrupts = ; > + reg = <0xf9028000 0x1000>; > + status = "disabled"; > + }; > + }; > + }; > + > + timer { > + compatible = "arm,armv7-timer"; > + interrupts = + (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>, > + + (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>, > + + (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>, > + + (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>; > + clock-frequency = <19200000>; > + }; > +}; > -- > 2.25.1 >