From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C1D23C433ED for ; Sat, 15 May 2021 21:48:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8F72361352 for ; Sat, 15 May 2021 21:48:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235152AbhEOVta (ORCPT ); Sat, 15 May 2021 17:49:30 -0400 Received: from perceval.ideasonboard.com ([213.167.242.64]:33902 "EHLO perceval.ideasonboard.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235133AbhEOVt3 (ORCPT ); Sat, 15 May 2021 17:49:29 -0400 Received: from pendragon.ideasonboard.com (62-78-145-57.bb.dnainternet.fi [62.78.145.57]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id E53CD436; Sat, 15 May 2021 23:48:14 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1621115295; bh=3HDfMZnFR3gpMA8k29TFZe4vdG02tiejMNDF+HfebMc=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=O0Tcm91ua7Gr4QLSDXPAVeEqzKH/KAAP0oxM3mnYgAEj9jnwAbW9DcknsHaRDEM50 NXximMjWZX4VhDRAD1FyMClFGHAz6UfFVk90seQs4f40F7gBcoM5luosQtsPNaWVrm QTG9/24e/iSxDx0HKV7OVCiTTckSMRLUAQlizfzk= Date: Sun, 16 May 2021 00:48:05 +0300 From: Laurent Pinchart To: Marek Vasut Cc: dri-devel@lists.freedesktop.org, ch@denx.de, Rob Herring , Sam Ravnborg , devicetree@vger.kernel.org Subject: Re: [PATCH] dt-bindings: display: bridge: lvds-codec: Fix spacing Message-ID: References: <20210515203932.366799-1-marex@denx.de> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20210515203932.366799-1-marex@denx.de> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Marek, Thank you for the patch. On Sat, May 15, 2021 at 10:39:32PM +0200, Marek Vasut wrote: > Add missing spaces to make the diagrams readable, no functional change. Looks better indeed. The patch view looks bad though, because of the tabs. Maybe you could replace them with spaces, while at it ? Reviewed-by: Laurent Pinchart > Signed-off-by: Marek Vasut > Cc: Laurent Pinchart > Cc: Rob Herring > Cc: Sam Ravnborg > Cc: devicetree@vger.kernel.org > To: dri-devel@lists.freedesktop.org > --- > .../devicetree/bindings/display/panel/lvds.yaml | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/Documentation/devicetree/bindings/display/panel/lvds.yaml b/Documentation/devicetree/bindings/display/panel/lvds.yaml > index 31164608ba1d..06d7ca692d0d 100644 > --- a/Documentation/devicetree/bindings/display/panel/lvds.yaml > +++ b/Documentation/devicetree/bindings/display/panel/lvds.yaml > @@ -52,9 +52,9 @@ properties: > [VESA] specifications. Data are transferred as follows on 3 LVDS lanes. > > Slot 0 1 2 3 4 5 6 > - ________________ _________________ > + ________________ _________________ > Clock \_______________________/ > - ______ ______ ______ ______ ______ ______ ______ > + ______ ______ ______ ______ ______ ______ ______ > DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__>< > DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__>< > DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__>< > @@ -63,9 +63,9 @@ properties: > specifications. Data are transferred as follows on 4 LVDS lanes. > > Slot 0 1 2 3 4 5 6 > - ________________ _________________ > + ________________ _________________ > Clock \_______________________/ > - ______ ______ ______ ______ ______ ______ ______ > + ______ ______ ______ ______ ______ ______ ______ > DATA0 ><__G2__><__R7__><__R6__><__R5__><__R4__><__R3__><__R2__>< > DATA1 ><__B3__><__B2__><__G7__><__G6__><__G5__><__G4__><__G3__>< > DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B7__><__B6__><__B5__><__B4__>< > @@ -75,9 +75,9 @@ properties: > Data are transferred as follows on 4 LVDS lanes. > > Slot 0 1 2 3 4 5 6 > - ________________ _________________ > + ________________ _________________ > Clock \_______________________/ > - ______ ______ ______ ______ ______ ______ ______ > + ______ ______ ______ ______ ______ ______ ______ > DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__>< > DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__>< > DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__>< -- Regards, Laurent Pinchart