From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 77701C47082 for ; Thu, 3 Jun 2021 15:34:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 54D45613F4 for ; Thu, 3 Jun 2021 15:34:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229778AbhFCPgY (ORCPT ); Thu, 3 Jun 2021 11:36:24 -0400 Received: from mx01.ayax.eu ([188.137.98.110]:41572 "EHLO mx01.ayax.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229617AbhFCPgY (ORCPT ); Thu, 3 Jun 2021 11:36:24 -0400 Received: from [192.168.192.146] (port=48286 helo=nx64de-df6d00) by mx01.ayax.eu with esmtpsa (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lopMR-0005wd-L7; Thu, 03 Jun 2021 17:34:19 +0200 Date: Thu, 3 Jun 2021 17:34:18 +0200 From: Grzegorz Szymaszek To: Alexandre Torgue , Maxime Coquelin Cc: Grzegorz Szymaszek , Ahmad Fatoum , Marcin Sloniewski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v2] ARM: dts: stm32: add a new DCMI pins group Message-ID: Mail-Followup-To: Grzegorz Szymaszek , Alexandre Torgue , Maxime Coquelin , Ahmad Fatoum , Marcin Sloniewski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Seeed Odyssey-STM32MP157C board has a 20-pin DVP camera output. stm32mp15-pinctrl.dtsi contained one pin state definition for the DCMI interface, dcmi-0, AKA phandle dcmi_pins_a. This definition was incompatible with the pins used on the Odyssey board, where: - there are 8 data pins instead of 12, - DCMI_HSYNC is available at PA4 instead of PH8, - DCMI_D0 is at PC6 instead of PH9, - DCMI_D3 is at PE1 instead of PH12, - DCMI_D4 is at PE11 instead of PH14, - DCMI_D5 is at PD3 instead of PI4, - DCMI_D6 is at PE13 instead of PB8, - DCMI_D7 is at PB9 instead of PE6. Add the DCMI pins used on the Odyssey board as a new DCMI pin state definition, dcmi-1, AKA phandle dcmi_pins_b. Signed-off-by: Grzegorz Szymaszek --- V1 -> V2: Removed the pinctrl override from the Odyssey device tree, added a new pinctrl in stm32mp15-pinctrl.dtsi instead arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 33 ++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index 060baa8b7e9d..5b60ecbd718f 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -118,6 +118,39 @@ pins { }; }; + dcmi_pins_b: dcmi-1 { + pins { + pinmux = ,/* DCMI_HSYNC */ + ,/* DCMI_VSYNC */ + ,/* DCMI_PIXCLK */ + ,/* DCMI_D0 */ + ,/* DCMI_D1 */ + ,/* DCMI_D2 */ + ,/* DCMI_D3 */ + ,/* DCMI_D4 */ + ,/* DCMI_D5 */ + ,/* DCMI_D6 */ + ;/* DCMI_D7 */ + bias-disable; + }; + }; + + dcmi_sleep_pins_b: dcmi-sleep-1 { + pins { + pinmux = ,/* DCMI_HSYNC */ + ,/* DCMI_VSYNC */ + ,/* DCMI_PIXCLK */ + ,/* DCMI_D0 */ + ,/* DCMI_D1 */ + ,/* DCMI_D2 */ + ,/* DCMI_D3 */ + ,/* DCMI_D4 */ + ,/* DCMI_D5 */ + ,/* DCMI_D6 */ + ;/* DCMI_D7 */ + }; + }; + ethernet0_rgmii_pins_a: rgmii-0 { pins1 { pinmux = , /* ETH_RGMII_CLK125 */ -- 2.30.2