From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 00240C49EA4 for ; Wed, 23 Jun 2021 13:15:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C866361075 for ; Wed, 23 Jun 2021 13:15:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230206AbhFWNRc (ORCPT ); Wed, 23 Jun 2021 09:17:32 -0400 Received: from perceval.ideasonboard.com ([213.167.242.64]:38832 "EHLO perceval.ideasonboard.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230182AbhFWNRb (ORCPT ); Wed, 23 Jun 2021 09:17:31 -0400 Received: from pendragon.ideasonboard.com (62-78-145-57.bb.dnainternet.fi [62.78.145.57]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id EDAA69AA; Wed, 23 Jun 2021 15:15:11 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1624454112; bh=GVMK38SrPGTYbsOKUOPXSrEWY3ARN0rb2JGcAOPGBtQ=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=sd76KXBNzmD/7FV+Gt4wR9mi4Lxk/zMoruxdN9MF5tC8iXo8ltWBUF35E1592qlms jN8Na4J3N87rM+phQYcEEJTQ1uGI1z0adgrZhbaygPV3/NXk9Co5H+OQZsMDv3lMJ0 XmoXHC9TPgp4lAqcG56vFOC6WVe7hFc/7DIUThxE= Date: Wed, 23 Jun 2021 16:14:42 +0300 From: Laurent Pinchart To: Geert Uytterhoeven Cc: Kieran Bingham , Kieran Bingham , David Airlie , Daniel Vetter , Rob Herring , "open list:DRM DRIVERS FOR RENESAS" , "open list:DRM DRIVERS FOR RENESAS" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , open list Subject: Re: [PATCH] dt-bindings: display: renesas,du: Provide bindings for r8a779a0 Message-ID: References: <20210622231146.3208404-1-kieran.bingham@ideasonboard.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Geert, On Wed, Jun 23, 2021 at 03:09:06PM +0200, Geert Uytterhoeven wrote: > On Wed, Jun 23, 2021 at 2:58 PM Laurent Pinchart wrote: > > On Wed, Jun 23, 2021 at 02:53:33PM +0200, Geert Uytterhoeven wrote: > > > On Wed, Jun 23, 2021 at 1:11 AM Kieran Bingham wrote: > > > > From: Kieran Bingham > > > > > > > > Extend the Renesas DU display bindings to support the r8a779a0 V3U. > > > > > > > > Signed-off-by: Kieran Bingham > > > > > > Thanks for your patch! > > > > > > > --- a/Documentation/devicetree/bindings/display/renesas,du.yaml > > > > +++ b/Documentation/devicetree/bindings/display/renesas,du.yaml > > > > @@ -39,6 +39,7 @@ properties: > > > > - renesas,du-r8a77980 # for R-Car V3H compatible DU > > > > - renesas,du-r8a77990 # for R-Car E3 compatible DU > > > > - renesas,du-r8a77995 # for R-Car D3 compatible DU > > > > + - renesas,du-r8a779a0 # for R-Car V3U compatible DU > > > > > > > > reg: > > > > maxItems: 1 > > > > @@ -774,6 +775,57 @@ allOf: > > > > - reset-names > > > > - renesas,vsps > > > > > > > > + - if: > > > > + properties: > > > > + compatible: > > > > + contains: > > > > + enum: > > > > + - renesas,du-r8a779a0 > > > > + then: > > > > + properties: > > > > + clocks: > > > > + items: > > > > + - description: Functional clock for DU0 > > > > + - description: Functional clock for DU1 > > > > + > > > > + clock-names: > > > > + items: > > > > + - const: du.0 > > > > + - const: du.1 > > > > > > The hardware block has only a single function clock for both channels, > > > like on R-Car H1. > > > > > > And what about DU_DOTCLKIN? > > > > As far as I can tell, there's no DU_DOTCLKIN in V3U. > > See Table 6.13 of the Hardware User's Manual, pin IPC_CLKIN. Maybe that's incorrect ? There's no mention of DU_DOTCLKIN anywhere else, and the DU bits that allow selection of the input clocks list the value documented for Gen3 SoCs as selected DU_DOTCLKIN as reserved. > Note that the register bits to configure it are present in > drivers/pinctrl/renesas/pfc-r8a779a0.c, but the actual pin group is > missing. -- Regards, Laurent Pinchart