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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id u7sm2263004oop.11.2021.07.25.11.27.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Jul 2021 11:27:15 -0700 (PDT) Date: Sun, 25 Jul 2021 13:27:13 -0500 From: Bjorn Andersson To: Baruch Siach , Rob Herring Cc: Thierry Reding , Uwe Kleine-K?nig , Lee Jones , Andy Gross , Balaji Prakash J , Robert Marko , Kathiravan T , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v6 3/4] dt-bindings: pwm: add IPQ6018 binding Message-ID: References: <889aae1b88f120cb6281919d27164a959fbe69d0.1626948070.git.baruch@tkos.co.il> <70f0522a9394e9da2f31871442d47f6ad0ff41aa.1626948070.git.baruch@tkos.co.il> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <70f0522a9394e9da2f31871442d47f6ad0ff41aa.1626948070.git.baruch@tkos.co.il> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Thu 22 Jul 05:01 CDT 2021, Baruch Siach wrote: > DT binding for the PWM block in Qualcomm IPQ6018 SoC. > > Signed-off-by: Baruch Siach > --- > v6: > > Device node is child of TCSR; remove phandle (Rob Herring) > > Add assigned-clocks/assigned-clock-rates (Uwe Kleine-König) > > v5: Use qcom,pwm-regs for phandle instead of direct regs (Bjorn > Andersson, Kathiravan T) > > v4: Update the binding example node as well (Rob Herring's bot) > > v3: s/qcom,pwm-ipq6018/qcom,ipq6018-pwm/ (Rob Herring) > > v2: Make #pwm-cells const (Rob Herring) > --- > .../devicetree/bindings/pwm/ipq-pwm.yaml | 69 +++++++++++++++++++ > 1 file changed, 69 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pwm/ipq-pwm.yaml > > diff --git a/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml b/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml > new file mode 100644 > index 000000000000..ee2bb03a1223 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml > @@ -0,0 +1,69 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pwm/ipq-pwm.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm IPQ6018 PWM controller > + > +maintainers: > + - Baruch Siach > + > +properties: > + "#pwm-cells": > + const: 2 > + > + compatible: > + const: qcom,ipq6018-pwm > + > + offset: > + description: | '|' maintains the formatting of the text, you don't need that. > + Offset of PWM register in the TCSR block. > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > + clock-names: > + const: core With a single clock, it's nice to skip the -names. > + > + assigned-clocks: > + maxItems: 1 > + > + assigned-clock-rates: > + maxItems: 1 These (assigned-*) are generic properties that may be used on a lot of nodes, should they really be part of the individual binding, Rob? > + > +required: > + - "#pwm-cells" > + - compatible > + - clocks > + - clock-names > + - assigned-clocks > + - assigned-clock-rates > + > +additionalProperties: false > + > +examples: > + - | > + #include > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + Skip soc and *-cells... > + tcsr: syscon@1937000 { > + compatible = "syscon", "simple-mfd"; > + reg = <0x0 0x01937000 0x0 0x21000>; > + ..and just make this "reg = <0x01937000 0x21000>", in the example. Then as we put this in the particular dts we adjust for whatever *-cells that has defined for the parent bus. > + pwm: pwm { > + #pwm-cells = <2>; I know it's important that this is a pwm thing, but I would prefer to see the node start with compatible, offset/reg, clocks. And then end with whatever is exposed (i.e. #pwm-cells) Regards, Bjorn > + compatible = "qcom,ipq6018-pwm"; > + offset = <0xa010>; > + clocks = <&gcc GCC_ADSS_PWM_CLK>; > + clock-names = "core"; > + assigned-clocks = <&gcc GCC_ADSS_PWM_CLK>; > + assigned-clock-rates = <100000000>; > + status = "disabled"; > + }; > + }; > + }; > -- > 2.30.2 >