[PATCH v6 3/4] dt-bindings: pwm: add IPQ6018 binding

Baruch Siach
2021-07-22T10:11:25Z

DT binding for the PWM block in Qualcomm IPQ6018 SoC.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
---
v6:

Device node is child of TCSR; remove phandle (Rob Herring)

Add assigned-clocks/assigned-clock-rates (Uwe Kleine-König)

v5: Use qcom,pwm-regs for phandle instead of direct regs (Bjorn
Andersson, Kathiravan T)

v4: Update the binding example node as well (Rob Herring's bot)

v3: s/qcom,pwm-ipq6018/qcom,ipq6018-pwm/ (Rob Herring)

v2: Make #pwm-cells const (Rob Herring)
---
.../devicetree/bindings/pwm/ipq-pwm.yaml | 69 +++++++++++++++++++
1 file changed, 69 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pwm/ipq-pwm.yaml

diff --git a/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml b/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml
new file mode 100644
index 000000000000..ee2bb03a1223
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/ipq-pwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm IPQ6018 PWM controller
+
+maintainers:
+ - Baruch Siach <baruch@tkos.co.il>
+
+properties:
+ "#pwm-cells":
+ const: 2
+
+ compatible:
+ const: qcom,ipq6018-pwm
+
+ offset:
+ description: |
+ Offset of PWM register in the TCSR block.
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: core
+
+ assigned-clocks:
+ maxItems: 1
+
+ assigned-clock-rates:
+ maxItems: 1
+
+required:
+ - "#pwm-cells"
+ - compatible
+ - clocks
+ - clock-names
+ - assigned-clocks
+ - assigned-clock-rates
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-ipq6018.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ tcsr: syscon@1937000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x0 0x01937000 0x0 0x21000>;
+
+ pwm: pwm {
+ #pwm-cells = <2>;
+ compatible = "qcom,ipq6018-pwm";
+ offset = <0xa010>;
+ clocks = <&gcc GCC_ADSS_PWM_CLK>;
+ clock-names = "core";
+ assigned-clocks = <&gcc GCC_ADSS_PWM_CLK>;
+ assigned-clock-rates = <100000000>;
+ status = "disabled";
+ };
+ };
+ };
--
2.30.2