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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id c23sm539782otu.60.2021.08.17.12.15.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Aug 2021 12:15:18 -0700 (PDT) Received: (nullmailer pid 686682 invoked by uid 1000); Tue, 17 Aug 2021 19:15:17 -0000 Date: Tue, 17 Aug 2021 14:15:17 -0500 From: Rob Herring To: Jacky Bai Cc: shawnguo@kernel.org, abel.vesa@nxp.com, sboyd@kernel.org, s.hauer@pengutronix.de, p.zabel@pengutronix.de, kernel@pengutronix.de, linux-imx@nxp.com, devicetree@vger.kernel.org Subject: Re: [PATCH v2 1/9] dt-bindings: clock: Add imx8ulp clock support Message-ID: References: <20210810062820.1062884-1-ping.bai@nxp.com> <20210810062820.1062884-2-ping.bai@nxp.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210810062820.1062884-2-ping.bai@nxp.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Tue, Aug 10, 2021 at 02:28:12PM +0800, Jacky Bai wrote: > Add the clock dt-binding file for i.MX8ULP. > > For pcc node, it will also be used as a reset controller, > so add the '#reset-cells' property description and add the > pcc reset IDs. > > Signed-off-by: Jacky Bai > --- > v2 changes: > - removed the redundant clocks & clock-names property > > v1 changes: > - Move this patch from dts patchset into this patchset > --- > .../bindings/clock/imx8ulp-clock.yaml | 71 +++++ > include/dt-bindings/clock/imx8ulp-clock.h | 258 ++++++++++++++++++ > include/dt-bindings/reset/imx8ulp-pcc-reset.h | 59 ++++ > 3 files changed, 388 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/imx8ulp-clock.yaml > create mode 100644 include/dt-bindings/clock/imx8ulp-clock.h > create mode 100644 include/dt-bindings/reset/imx8ulp-pcc-reset.h > > diff --git a/Documentation/devicetree/bindings/clock/imx8ulp-clock.yaml b/Documentation/devicetree/bindings/clock/imx8ulp-clock.yaml > new file mode 100644 > index 000000000000..9a075de1086a > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/imx8ulp-clock.yaml > @@ -0,0 +1,71 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/imx8ulp-clock.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: NXP i.MX8ULP Clock Control Module Binding > + > +maintainers: > + - Jacky Bai > + > +description: | > + On i.MX8ULP, The clock sources generation, distribution and management is > + under the control of several CGCs & PCCs modules. The CGC modules generate > + and distribute clocks on the device. PCC modules control software reset, > + clock selection, optional division and clock gating mode for peripherals. > + > +properties: > + compatible: > + enum: > + - fsl,imx8ulp-cgc1 > + - fsl,imx8ulp-cgc2 > + - fsl,imx8ulp-pcc3 > + - fsl,imx8ulp-pcc4 > + - fsl,imx8ulp-pcc5 > + > + reg: > + maxItems: 1 > + > + '#clock-cells': > + const: 1 > + > + '#reset-cells': > + const: 1 > + > +required: > + - compatible > + - reg > + - '#clock-cells' > + > +allOf: > + - if: > + properties: > + compatible: > + contains: > + enum: > + - fsl,imx8ulp-pcc3 > + - fsl,imx8ulp-pcc4 > + - fsl,imx8ulp-pcc5 > + then: > + required: > + - '#reset-cells' And #reset-cells is optional for a CGC? I think this should be 2 schema files. There's nothing really shared any more than any other clock/reset controller. > + > +additionalProperties: false > + > +examples: > + # Clock Control Module node: > + - | > + clock-controller@292c0000 { > + compatible = "fsl,imx8ulp-cgc1"; > + reg = <0x292c0000 0x10000>; > + #clock-cells = <1>; > + }; > + > + - | > + clock-controller@292d0000 { > + compatible = "fsl,imx8ulp-pcc3"; > + reg = <0x292d0000 0x10000>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + };