From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0FD8EC43214 for ; Tue, 31 Aug 2021 15:30:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E8FB161053 for ; Tue, 31 Aug 2021 15:30:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239225AbhHaPbU (ORCPT ); Tue, 31 Aug 2021 11:31:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52192 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239297AbhHaPbT (ORCPT ); Tue, 31 Aug 2021 11:31:19 -0400 Received: from mail-pl1-x635.google.com (mail-pl1-x635.google.com [IPv6:2607:f8b0:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 57426C061764 for ; Tue, 31 Aug 2021 08:30:24 -0700 (PDT) Received: by mail-pl1-x635.google.com with SMTP id q21so10855550plq.3 for ; Tue, 31 Aug 2021 08:30:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=/8QKngx6fYNXsVFXUD7bTIuyP3AXKmtCfncJgPUlXPI=; b=fC56+C0qMUV2NToCVEr2JQ+mW+2KLQnLhMtgiO+yyGK4Ur9jxb8KUtHA66mMKGpXxs JkEXpXSPjcq7Slcubo26ZeFQFgbt+1zfU3ZQS4G61g/Sxjo5xGSPT/gmEIOOOD+2TuAj I8jOxkYk7LxEjigOMuC5S2EB0uMxZWQ7HVh98= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=/8QKngx6fYNXsVFXUD7bTIuyP3AXKmtCfncJgPUlXPI=; b=FI2cYBiu+CBGGU9QEds/qsilti/9JoorjQWb7Of8+Y6BvgjzHCB9R52fRBV45U4JH5 st+9eZ8hJwuISgoSkixeaio1SS/bZXvmWSEtXNg5y0I0qBN7hzLCOxX+08srt0b6SmG4 QGxFJBuHQ04DD2aDSPOEe/Nisy3b703gTYYuzdvxFJzwM7eEB8ynuTlHJshWk3opaqJ4 DRqWp26Qwfy8zePGYop9UTX7UTZ3pex07wo1dohleTddnIYDb4WVHS2SOVZbARtcy4FB ilRWwHe12OEK+St4Rz5j7HX9SVGWyIoW5WIIly7K7y4JCS3NWLoOZBmr2HiSm3LAmxlM UDDA== X-Gm-Message-State: AOAM530lqPA45txGu7YVPsMsQqiNgzUZlZwF3RhIuseAUx7GKk495yCf Dg8e1i+VJ0BilvNGLEbUW6E4EQ== X-Google-Smtp-Source: ABdhPJyIV524Xbc92XY555Tmny00GEGV8W56zWD1B0FkYhPwvzmWPRooO++MCwvgJJwBllurndNS1g== X-Received: by 2002:a17:902:6846:b0:138:eea0:9261 with SMTP id f6-20020a170902684600b00138eea09261mr2824106pln.12.1630423823864; Tue, 31 Aug 2021 08:30:23 -0700 (PDT) Received: from localhost ([2620:15c:202:201:12d4:6054:aa38:6fe2]) by smtp.gmail.com with UTF8SMTPSA id g12sm3306711pjh.33.2021.08.31.08.30.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 31 Aug 2021 08:30:23 -0700 (PDT) Date: Tue, 31 Aug 2021 08:30:21 -0700 From: Matthias Kaehlcke To: Sibi Sankar Cc: sboyd@kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org, viresh.kumar@linaro.org, agross@kernel.org, rjw@rjwysocki.net, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dianders@chromium.org, tdas@codeaurora.org Subject: Re: [PATCH 3/4] arm64: dts: qcom: sc7280: Fixup the cpufreq node Message-ID: References: <1627581885-32165-1-git-send-email-sibis@codeaurora.org> <1627581885-32165-4-git-send-email-sibis@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <1627581885-32165-4-git-send-email-sibis@codeaurora.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Thu, Jul 29, 2021 at 11:34:44PM +0530, Sibi Sankar wrote: > Fixup the register regions used by the cpufreq node on SC7280 SoC to > support per core L3 DCVS. > > Fixes: 7dbd121a2c58 ("arm64: dts: qcom: sc7280: Add cpufreq hw node") > Signed-off-by: Sibi Sankar This patch landed in the Bjorn's tree, however the corresponding driver change ("cpufreq: qcom: Re-arrange register offsets to support per core L3 DCVS" / https://patchwork.kernel.org/project/linux-arm-msm/patch/1627581885-32165-3-git-send-email-sibis@codeaurora.org/) did not land in any maintainer tree yet AFAIK. IIUC the DT change alone breaks cpufreq since the changed register regions require the changed offset in the cpufreq driver. Sibi, please confirm or clarify that my concern is unwarranted.