From: Alexandre Belloni <alexandre.belloni@bootlin.com>
To: Claudiu Beznea <claudiu.beznea@microchip.com>
Cc: nicolas.ferre@microchip.com, ludovic.desroches@microchip.com,
robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 0/3] ARM: dts: at91: enable ips for sama7g5
Date: Mon, 23 Aug 2021 14:18:44 +0200 [thread overview]
Message-ID: <YSOSJK0FmbgNynRc@piout.net> (raw)
In-Reply-To: <20210823100356.22206-1-claudiu.beznea@microchip.com>
On 23/08/2021 13:03:53+0300, Claudiu Beznea wrote:
> Hi,
>
> The following patches enable UDDRC, DDR3 PHY, SECURAM and SHDWC IPs
> on SAMA7G5.
>
> Thank you,
> Claudiu Beznea
>
> Claudiu Beznea (3):
> ARM: dts: at91: add ram bindings
> ARM: dts: at91: add bindins for securam
> ARM: dts: at91: add bindings for shdwc
I think you meant node instead of bindings.
--
Alexandre Belloni, co-owner and COO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
prev parent reply other threads:[~2021-08-23 12:18 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-23 10:03 [PATCH 0/3] ARM: dts: at91: enable ips for sama7g5 Claudiu Beznea
2021-08-23 10:03 ` [PATCH 1/3] ARM: dts: at91: add ram bindings Claudiu Beznea
2021-08-23 10:03 ` [PATCH 2/3] ARM: dts: at91: add bindins for securam Claudiu Beznea
2021-08-23 10:03 ` [PATCH 3/3] ARM: dts: at91: add bindings for shdwc Claudiu Beznea
2021-08-23 12:18 ` Alexandre Belloni [this message]
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