[PATCH v7 0/3] Add RZ/G2L DMAC support

[PATCH v7 0/3] Add RZ/G2L DMAC support

[Biju Das]

This patch series aims to add DMAC support on RZ/G2L SoC's.

It is based on the work done by Chris Brandt for RZ/A DMA driver.

v6->v7:
 * As per the DMA documention vc.lock must be held by caller for
   vchan_cookie_complete. So added vc.lock for this function.
 * Added lock for the lists used in rz_dmac_terminate_all.

v5->v6:
 * Added Rb tag from Rob for binding patch
 * Fixed dma_addr_t and size_t format specifier issue reported by
   kernel test robot
 * Started using ARRAY_SIZE macro instead of  magic number in
   rz_dmac_ds_to_val_mapping function.

v4->v5:
 * Passing legacy slave channel configuration parameters using dmaengine_slave_config is prohibited.
   So started passing this parameters in DT instead, by encoding MID/RID values with channel parameters
   in the #dma-cells.
 * Removed Rb tag's of Geert and Rob since there is a modification in binding patch
 * Added 128 byte slave bus width support
 * Removed SoC dtsi and Defconfig patch from this series. Will send as separate patch.

Ref:-
  https://lore.kernel.org/linux-renesas-soc/20210719092535.4474-1-biju.das.jz@bp.renesas.com/T/#ma0b261df6d4400882204aaaaa014ddb59c479db4

v3->v4:
 * Added Rob's Rb tag for binding patch.
 * Incorporated Vinod and Geert's review comments.
v2->v3:
  * Described clocks and resets in binding file as per Rob's feedback.

v1->v2
 * Started using virtual DMAC
 * Added Geert's Rb tag for binding patch.

Biju Das (3):
  dt-bindings: dma: Document RZ/G2L bindings
  dmaengine: Extend the dma_slave_width for 128 bytes
  drivers: dma: sh: Add DMAC driver for RZ/G2L SoC

 .../bindings/dma/renesas,rz-dmac.yaml         | 130 +++
 drivers/dma/sh/Kconfig                        |   9 +
 drivers/dma/sh/Makefile                       |   1 +
 drivers/dma/sh/rz-dmac.c                      | 971 ++++++++++++++++++
 include/linux/dmaengine.h                     |   3 +-
 5 files changed, 1113 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
 create mode 100644 drivers/dma/sh/rz-dmac.c

-- 
2.17.1

[PATCH v7 1/3] dt-bindings: dma: Document RZ/G2L bindings

[Biju Das]

Document RZ/G2L DMAC bindings.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Note:-
 This base series for this patch is Linux 5.14-rc2(or +) otherwise bots would 
 complain about check failures

v6->v7:
  * No Change.
v5->v6:
  * No Change. Added Rb tag from Rob.
v4->v5:
  * Passing legacy slave channel configuration parameters using dmaengine_slave_config is prohibited.
    So started passing this parameters in DT instead, by encoding MID/RID values with channel parameters
    in the #dma-cells.
  * Updated the description for #dma-cells
  * Removed Rb tag's of Geert and Rob since there is a modification in binding patch
v3->v4:
  * Added Rob's Rb tag
  * Described clocks and reset properties
v2->v3:
  * Added error interrupt first.
  * Updated clock and reset maxitems.
  * Added Geert's Rb tag.
v1->v2:
  * Made interrupt names in defined order
  * Removed src address and channel configuration from dma-cells.
  * Changed the compatibele string to "renesas,r9a07g044-dmac".
v1:-
  * https://patchwork.kernel.org/project/linux-renesas-soc/patch/20210611113642.18457-2-biju.das.jz@bp.renesas.com/
---
 .../bindings/dma/renesas,rz-dmac.yaml         | 130 ++++++++++++++++++
 1 file changed, 130 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml

diff --git a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
new file mode 100644
index 000000000000..7a4f415d74dc
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
@@ -0,0 +1,130 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/renesas,rz-dmac.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/G2L DMA Controller
+
+maintainers:
+  - Biju Das <biju.das.jz@bp.renesas.com>
+
+allOf:
+  - $ref: "dma-controller.yaml#"
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - renesas,r9a07g044-dmac # RZ/G2{L,LC}
+      - const: renesas,rz-dmac
+
+  reg:
+    items:
+      - description: Control and channel register block
+      - description: DMA extended resource selector block
+
+  interrupts:
+    maxItems: 17
+
+  interrupt-names:
+    items:
+      - const: error
+      - const: ch0
+      - const: ch1
+      - const: ch2
+      - const: ch3
+      - const: ch4
+      - const: ch5
+      - const: ch6
+      - const: ch7
+      - const: ch8
+      - const: ch9
+      - const: ch10
+      - const: ch11
+      - const: ch12
+      - const: ch13
+      - const: ch14
+      - const: ch15
+
+  clocks:
+    items:
+      - description: DMA main clock
+      - description: DMA register access clock
+
+  '#dma-cells':
+    const: 1
+    description:
+      The cell specifies the encoded MID/RID values of the DMAC port
+      connected to the DMA client and the slave channel configuration
+      parameters.
+      bits[0:9] - Specifies MID/RID value
+      bit[10] - Specifies DMA request high enable (HIEN)
+      bit[11] - Specifies DMA request detection type (LVL)
+      bits[12:14] - Specifies DMAACK output mode (AM)
+      bit[15] - Specifies Transfer Mode (TM)
+
+  dma-channels:
+    const: 16
+
+  power-domains:
+    maxItems: 1
+
+  resets:
+    items:
+      - description: Reset for DMA ARESETN reset terminal
+      - description: Reset for DMA RST_ASYNC reset terminal
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - interrupt-names
+  - clocks
+  - '#dma-cells'
+  - dma-channels
+  - power-domains
+  - resets
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/r9a07g044-cpg.h>
+
+    dmac: dma-controller@11820000 {
+        compatible = "renesas,r9a07g044-dmac",
+                     "renesas,rz-dmac";
+        reg = <0x11820000 0x10000>,
+              <0x11830000 0x10000>;
+        interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
+        interrupt-names = "error",
+                          "ch0", "ch1", "ch2", "ch3",
+                          "ch4", "ch5", "ch6", "ch7",
+                          "ch8", "ch9", "ch10", "ch11",
+                          "ch12", "ch13", "ch14", "ch15";
+        clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>,
+                 <&cpg CPG_MOD R9A07G044_DMAC_PCLK>;
+        power-domains = <&cpg>;
+        resets = <&cpg R9A07G044_DMAC_ARESETN>,
+                 <&cpg R9A07G044_DMAC_RST_ASYNC>;
+        #dma-cells = <1>;
+        dma-channels = <16>;
+    };
-- 
2.17.1

RE: [PATCH v7 0/3] Add RZ/G2L DMAC support

[Biju Das]

Hi All,

Gentle ping. Are we happy with this patch series? Please let me know.

Regards,
Biju

> Subject: [PATCH v7 0/3] Add RZ/G2L DMAC support
> 
> This patch series aims to add DMAC support on RZ/G2L SoC's.
> 
> It is based on the work done by Chris Brandt for RZ/A DMA driver.
> 
> v6->v7:
>  * As per the DMA documention vc.lock must be held by caller for
>    vchan_cookie_complete. So added vc.lock for this function.
>  * Added lock for the lists used in rz_dmac_terminate_all.
> 
> v5->v6:
>  * Added Rb tag from Rob for binding patch
>  * Fixed dma_addr_t and size_t format specifier issue reported by
>    kernel test robot
>  * Started using ARRAY_SIZE macro instead of  magic number in
>    rz_dmac_ds_to_val_mapping function.
> 
> v4->v5:
>  * Passing legacy slave channel configuration parameters using
> dmaengine_slave_config is prohibited.
>    So started passing this parameters in DT instead, by encoding MID/RID
> values with channel parameters
>    in the #dma-cells.
>  * Removed Rb tag's of Geert and Rob since there is a modification in
> binding patch
>  * Added 128 byte slave bus width support
>  * Removed SoC dtsi and Defconfig patch from this series. Will send as
> separate patch.
> 
> Ref:-
> 
> https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.ker
> nel.org%2Flinux-renesas-soc%2F20210719092535.4474-1-
> biju.das.jz%40bp.renesas.com%2FT%2F%23ma0b261df6d4400882204aaaaa014ddb59c4
> 79db4&data=04%7C01%7Cbiju.das.jz%40bp.renesas.com%7Cc9ed17350b194896fc
> b308d958c00a1c%7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C63763840409343
> 0389%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6I
> k1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=y2phFowFQIsATfjN%2FagVsOsZU5fOVsn8Z
> maE3%2BvhUVo%3D&reserved=0
> 
> v3->v4:
>  * Added Rob's Rb tag for binding patch.
>  * Incorporated Vinod and Geert's review comments.
> v2->v3:
>   * Described clocks and resets in binding file as per Rob's feedback.
> 
> v1->v2
>  * Started using virtual DMAC
>  * Added Geert's Rb tag for binding patch.
> 
> Biju Das (3):
>   dt-bindings: dma: Document RZ/G2L bindings
>   dmaengine: Extend the dma_slave_width for 128 bytes
>   drivers: dma: sh: Add DMAC driver for RZ/G2L SoC
> 
>  .../bindings/dma/renesas,rz-dmac.yaml         | 130 +++
>  drivers/dma/sh/Kconfig                        |   9 +
>  drivers/dma/sh/Makefile                       |   1 +
>  drivers/dma/sh/rz-dmac.c                      | 971 ++++++++++++++++++
>  include/linux/dmaengine.h                     |   3 +-
>  5 files changed, 1113 insertions(+), 1 deletion(-)  create mode 100644
> Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
>  create mode 100644 drivers/dma/sh/rz-dmac.c
> 
> --
> 2.17.1

Re: [PATCH v7 0/3] Add RZ/G2L DMAC support

[Vinod Koul]

On 06-08-21, 10:53, Biju Das wrote:
> This patch series aims to add DMAC support on RZ/G2L SoC's.
> 
> It is based on the work done by Chris Brandt for RZ/A DMA driver.

Applied all after fixing the subsystem tag for patch 3!

-- 
~Vinod

RE: [PATCH v7 0/3] Add RZ/G2L DMAC support

[Biju Das]

> Subject: Re: [PATCH v7 0/3] Add RZ/G2L DMAC support
> 
> On 06-08-21, 10:53, Biju Das wrote:
> > This patch series aims to add DMAC support on RZ/G2L SoC's.
> >
> > It is based on the work done by Chris Brandt for RZ/A DMA driver.
> 
> Applied all after fixing the subsystem tag for patch 3!

Thanks Vinod.

Regards,
Biju(210 😊)