Re: [PATCH 1/3] arm: dts: qcom: apq8064: Use 27MHz PXO clock as DSI PLL reference

Marijn Suijten
2021-08-30T08:28:12Z

Hi Dmitry,

On 8/30/21 3:18 AM, Dmitry Baryshkov wrote:
> On Sun, 29 Aug 2021 at 23:30, Marijn Suijten
> <marijn.suijten@somainline.org> wrote:
>>
>> The 28NM DSI PLL driver for msm8960 calculates with a 27MHz reference
>> clock and should hence use PXO, not CXO which runs at 19.2MHz.
>>
>> Note that none of the DSI PHY/PLL drivers currently use this "ref"
>> clock; they all rely on (sometimes inexistant) global clock names and
>> usually function normally without a parent clock. This discrepancy will
>> be corrected in a future patch, for which this change needs to be in
>> place first.
>>
>> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
> Checked the downstream driver, it always uses 27 MHz clock in calculations.

Given our concerns for msm8974 not updating DT in parallel with the
kernel (hence the need for a global-name fallback because "ref" is
missing from the DT), should we worry about the same for apq8064? That
is, is there a chance that the kernel but not the firmware is upgraded
leading to the wrong parent clock being used? The msm8960 variant of
the 28nm PLL driver uses parent_rate in a few places and might read
cxo's 19.2MHz erroneously instead of using pxo's 27MHz.

- Marijn