From: Rob Herring <robh@kernel.org>
To: kavyasree.kotagiri@microchip.com
Cc: mturquette@baylibre.com, sboyd@kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-clk@vger.kernel.org, UNGLinuxDriver@microchip.com,
Eugen.Hristev@microchip.com, Manohar.Puri@microchip.com
Subject: Re: [PATCH 3/3] dt-bindings: clock: lan966x: Add LAN966X Clock Controller
Date: Tue, 7 Sep 2021 14:00:15 -0500 [thread overview]
Message-ID: <YTe2v8nQt36NyC/s@robh.at.kernel.org> (raw)
In-Reply-To: <20210902092954.28359-1-kavyasree.kotagiri@microchip.com>
On Thu, Sep 02, 2021 at 02:59:54PM +0530, kavyasree.kotagiri@microchip.com wrote:
> From: Kavyasree Kotagiri <Kavyasree.Kotagiri@microchip.com>
Ah, here's the rest. The threading of your series is broken.
>
> This adds the DT bindings documentation for lan966x SoC
> generic clock controller.
>
> Signed-off-by: Kavya Sree Kotagiri <kavyasree.kotagiri@microchip.com>
Please make your author and Sob name and email match.
> ---
> .../bindings/clock/microchip,lan966x-gck.yaml | 46 +++++++++++++++++++
> 1 file changed, 46 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml
>
> diff --git a/Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml b/Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml
> new file mode 100644
> index 000000000000..0df765f628c4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml
> @@ -0,0 +1,46 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/microchip,lan966x-gck.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Microchip LAN966X Generic Clock Controller
> +
> +maintainers:
> + - Kavya Sree Kotagiri <kavyasree.kotagiri@microchip.com>
> +
> +description: |
> + The LAN966X Generic clock controller contains 3 PLLs - cpu_clk,
> + ddr_clk and sys_clk. This clock controller generates and supplies
> + clock to various peripherals within the SoC.
> +
> +properties:
> + compatible:
> + const: microchip,lan966x-gck
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> + '#clock-cells':
> + const: 1
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - '#clock-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + clks: clock-controller@e00c00a8 {
> + compatible = "microchip,lan966x-gck";
> + #clock-cells = <1>;
> + clocks = <&cpu_clk>;
> + reg = <0xe00c00a8 0x38>;
Looks like this is part of some other block?
> + };
> +...
> --
> 2.17.1
>
>
prev parent reply other threads:[~2021-09-07 19:00 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-02 9:29 [PATCH 3/3] dt-bindings: clock: lan966x: Add LAN966X Clock Controller kavyasree.kotagiri
2021-09-07 19:00 ` Rob Herring [this message]
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