Re: [PATCH] dt-bindings: net: Add bindings for IXP4xx V.35 WAN HSS

[Rob Herring <robh@kernel.org>]

On Thu, Sep 09, 2021 at 12:11:18AM +0200, Linus Walleij wrote:
> This adds device tree bindings for the IXP4xx V.35 WAN high
> speed serial (HSS) link.
> 
> An example is added to the NPE example where the HSS appears
> as a child.
> 
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
> Currently only adding these bindings so we can describe the
> hardware in device trees.
> ---
>  ...ntel,ixp4xx-network-processing-engine.yaml |  26 ++++
>  .../bindings/net/intel,ixp4xx-hss.yaml        | 129 ++++++++++++++++++
>  2 files changed, 155 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/net/intel,ixp4xx-hss.yaml
> 
> diff --git a/Documentation/devicetree/bindings/firmware/intel,ixp4xx-network-processing-engine.yaml b/Documentation/devicetree/bindings/firmware/intel,ixp4xx-network-processing-engine.yaml
> index c435c9f369a4..179e5dea32b0 100644
> --- a/Documentation/devicetree/bindings/firmware/intel,ixp4xx-network-processing-engine.yaml
> +++ b/Documentation/devicetree/bindings/firmware/intel,ixp4xx-network-processing-engine.yaml
> @@ -45,9 +45,35 @@ additionalProperties: false
>  
>  examples:
>    - |
> +    #include <dt-bindings/gpio/gpio.h>
> +
>      npe: npe@c8006000 {
>           compatible = "intel,ixp4xx-network-processing-engine";
>           reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>;
> +         #address-cells = <1>;
> +         #size-cells = <0>;
> +
> +         hss@0 {
> +             compatible = "intel,ixp4xx-hss";
> +             reg = <0>;
> +             intel,npe-handle = <&npe 0>;
> +             queue-chl-rxtrig = <&qmgr 12>;
> +             queue-pkt-rx = <&qmgr 13>;
> +             queue-pkt-tx0 = <&qmgr 14>;
> +             queue-pkt-tx1 = <&qmgr 15>;
> +             queue-pkt-tx2 = <&qmgr 16>;
> +             queue-pkt-tx3 = <&qmgr 17>;
> +             queue-pkt-rxfree0 = <&qmgr 18>;
> +             queue-pkt-rxfree1 = <&qmgr 19>;
> +             queue-pkt-rxfree2 = <&qmgr 20>;
> +             queue-pkt-rxfree3 = <&qmgr 21>;
> +             queue-pkt-txdone = <&qmgr 22>;

Need vendor prefix on all these. Maybe some can be arrays (e.g. tx0, 
tx1, tx2, tx3)?

> +             cts-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
> +             rts-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
> +             dcd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
> +             dtr-gpios = <&gpio_74 2 GPIO_ACTIVE_LOW>;
> +             clk-internal-gpios = <&gpio_74 0 GPIO_ACTIVE_HIGH>;
> +         };
>  
>           crypto {
>               compatible = "intel,ixp4xx-crypto";
> diff --git a/Documentation/devicetree/bindings/net/intel,ixp4xx-hss.yaml b/Documentation/devicetree/bindings/net/intel,ixp4xx-hss.yaml
> new file mode 100644
> index 000000000000..a5a9a14a1242
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/intel,ixp4xx-hss.yaml
> @@ -0,0 +1,129 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +# Copyright 2021 Linaro Ltd.
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/net/intel,ixp4xx-hss.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Intel IXP4xx V.35 WAN High Speed Serial Link (HSS)
> +
> +maintainers:
> +  - Linus Walleij <linus.walleij@linaro.org>
> +
> +description: |
> +  The Intel IXP4xx HSS makes use of the IXP4xx NPE (Network
> +  Processing Engine) and the IXP4xx Queue Manager to process
> +  V.35 Wideband Modem (WAN) links.
> +
> +properties:
> +  compatible:
> +    const: intel,ixp4xx-hss
> +
> +  reg:
> +    maxItems: 1
> +    description: The HSS instance
> +
> +  intel,npe-handle:
> +    $ref: '/schemas/types.yaml#/definitions/phandle-array'
> +    maxItems: 1
> +    description: phandle to the NPE this HSS instance is using
> +      and the instance to use in the second cell
> +
> +  queue-chl-rxtrig:
> +    $ref: '/schemas/types.yaml#/definitions/phandle-array'
> +    maxItems: 1
> +    description: phandle to the RX trigger queue on the NPE
> +
> +  queue-pkt-rx:
> +    $ref: '/schemas/types.yaml#/definitions/phandle-array'
> +    maxItems: 1
> +    description: phandle to the packet RX queue on the NPE
> +
> +  queue-pkt-tx0:
> +    $ref: '/schemas/types.yaml#/definitions/phandle-array'
> +    maxItems: 1
> +    description: phandle to the packet TX0 queue on the NPE
> +
> +  queue-pkt-tx1:
> +    $ref: '/schemas/types.yaml#/definitions/phandle-array'
> +    maxItems: 1
> +    description: phandle to the packet TX1 queue on the NPE
> +
> +  queue-pkt-tx2:
> +    $ref: '/schemas/types.yaml#/definitions/phandle-array'
> +    maxItems: 1
> +    description: phandle to the packet TX2 queue on the NPE
> +
> +  queue-pkt-tx3:
> +    $ref: '/schemas/types.yaml#/definitions/phandle-array'
> +    maxItems: 1
> +    description: phandle to the packet TX3 queue on the NPE
> +
> +  queue-pkt-rxfree0:
> +    $ref: '/schemas/types.yaml#/definitions/phandle-array'
> +    maxItems: 1
> +    description: phandle to the packet RXFREE0 queue on the NPE
> +
> +  queue-pkt-rxfree1:
> +    $ref: '/schemas/types.yaml#/definitions/phandle-array'
> +    maxItems: 1
> +    description: phandle to the packet RXFREE1 queue on the NPE
> +
> +  queue-pkt-rxfree2:
> +    $ref: '/schemas/types.yaml#/definitions/phandle-array'
> +    maxItems: 1
> +    description: phandle to the packet RXFREE2 queue on the NPE
> +
> +  queue-pkt-rxfree3:
> +    $ref: '/schemas/types.yaml#/definitions/phandle-array'
> +    maxItems: 1
> +    description: phandle to the packet RXFREE3 queue on the NPE
> +
> +  queue-pkt-txdone:
> +    $ref: '/schemas/types.yaml#/definitions/phandle-array'
> +    maxItems: 1
> +    description: phandle to the packet TXDONE queue on the NPE
> +
> +  cts-gpios:
> +    maxItems: 1
> +    description: Clear To Send (CTS) GPIO line
> +
> +  rts-gpios:
> +    maxItems: 1
> +    description: Ready To Send (RTS) GPIO line
> +
> +  dcd-gpios:
> +    maxItems: 1
> +    description: Data Carrier Detect (DCD) GPIO line
> +
> +  dtr-gpios:
> +    maxItems: 1
> +    description: Data Terminal Ready (DTR) GPIO line
> +
> +  clk-internal-gpios:
> +    maxItems: 1
> +    description: Clock internal GPIO line, driving this high will make the HSS
> +      use internal clocking as opposed to external clocking
> +
> +required:
> +  - compatible
> +  - reg
> +  - intel,npe-handle
> +  - queue-chl-rxtrig
> +  - queue-pkt-rx
> +  - queue-pkt-tx0
> +  - queue-pkt-tx1
> +  - queue-pkt-tx2
> +  - queue-pkt-tx3
> +  - queue-pkt-rxfree0
> +  - queue-pkt-rxfree1
> +  - queue-pkt-rxfree2
> +  - queue-pkt-rxfree3
> +  - queue-pkt-txdone
> +  - cts-gpios
> +  - rts-gpios
> +  - dcd-gpios
> +  - dtr-gpios
> +  - clk-internal-gpios
> +
> +additionalProperties: false
> -- 
> 2.31.1
> 
>