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Tue, 14 Sep 2021 11:29:23 +0000 Date: Tue, 14 Sep 2021 14:29:20 +0300 From: Abel Vesa To: Jacky Bai Cc: shawnguo@kernel.org, robh+dt@kernel.org, sboyd@kernel.org, s.hauer@pengutronix.de, p.zabel@pengutronix.de, kernel@pengutronix.de, linux-imx@nxp.com, devicetree@vger.kernel.org Subject: Re: [PATCH v3 2/9] clk: imx: Update the pllv4 to support imx8ulp Message-ID: References: <20210914065208.3582128-1-ping.bai@nxp.com> <20210914065208.3582128-3-ping.bai@nxp.com> Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210914065208.3582128-3-ping.bai@nxp.com> X-ClientProxiedBy: VI1PR04CA0080.eurprd04.prod.outlook.com (2603:10a6:803:64::15) To VI1PR0401MB2559.eurprd04.prod.outlook.com (2603:10a6:800:57::8) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from ryzen (188.25.164.198) by VI1PR04CA0080.eurprd04.prod.outlook.com (2603:10a6:803:64::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4500.15 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?3MtPPhXL+MyqKKyB690EOFhf00D3HNY5v3cF/vj7ASK4X+YUFHwQUwnm0j3k?= =?us-ascii?Q?SCvKYw6fZIdSTSmdkv0xBKNInzOE3cgSX9A6dl1tc9CM+06kwbzG48+Vn6vw?= =?us-ascii?Q?6tXIlrKH1rCMJS1wowuMDdCnSc5dhrsbsarSGLVh91Elza27Na5hbaJArhVR?= =?us-ascii?Q?PiDfZTp9px1xmPkw4TyawSAUmaKHCbLg28uhfqsULxgKKKiPfFlkZJiFVQuU?= =?us-ascii?Q?KElbLmSWRDy38H19X/expsF/t+BDizR5s1IolGSwuBB4baJfAkuAaHt/bICm?= =?us-ascii?Q?QlloCu1Q3QEdJsGUHo6WKj8r6wDucbuCxu9Qox+d/U9Lemkoemj2azSNiLN6?= =?us-ascii?Q?KHKuvcDbh08Op/ltEgSB7yczzaU4KwMGZV/mS+6eXsMwnGa/TvD3c89ywcUy?= =?us-ascii?Q?OZ+/dfHGJSYosE1Bla0vQa+GBERS5Osj9j25YfMbEoTNVyH00MUDiKS744eL?= =?us-ascii?Q?hkqXGaNtfqIu8ouwMK4Vtj44uodr9ig0gROag2CA640w4yrPFmPkCNkccsKW?= =?us-ascii?Q?ppzXSg9SqtCLuE2G/2DpGxTSjU0OwzqtRCbdWdMhRkGKGrIH0P6MH4T8CPDc?= =?us-ascii?Q?iK5DDxXkr9KlxDCYyG6QLrj1cjSb2toNEnLVSMVoKwBjCYj3ZjctofiWZ4hR?= =?us-ascii?Q?6DWbzaKf+i5J1AmXqA2zx7y/F1O5k+tO0mQHcG1z+QnX7YmAux0m9dW3gSmA?= =?us-ascii?Q?rq0AtkDmLdd36b1OOC5WIAH42+CzxFHDxeHxpz9IGJcVt3Nkx+0JVarlgAju?= =?us-ascii?Q?x8ydgtv4Jd7kHbi+xeNFQD+vXIGqFtQYbOIFEOO7eQpsOQ7/5bjNh9+bL9QK?= =?us-ascii?Q?WocvwQPmrZTwMWmiWcjinrmJzOVkiJvyTgHdTcWzOG11+jZ03gDxuEIrsaRV?= =?us-ascii?Q?VvUZCgOsgdNzudf0YUju1vTbcFpB0xobVBrOB5SXdueSlzSc/Ebl7XaVtJRe?= =?us-ascii?Q?xrvOyrSETti0xJnq8rKvH3i8aJbj3Y48ZpVXxmbr7sAncHcdHOtCr9xwrQdq?= =?us-ascii?Q?6c7+i9p2TQx53v/MBW2rfRtDf8eNl/40ZDDzv7EkAPv4nRjRYdOiJHxTCBdy?= =?us-ascii?Q?0CmxP3H/RVL9F4Aybj5blJkfT80oJOLach1/kLTtruWgbBh4+G6tDUTrKGcK?= =?us-ascii?Q?qxyxKDnLDkp8ftEfiFas1Osa/sB4Xpq7EznGCFaAJpHGEgr3/uAMctcRCeZY?= =?us-ascii?Q?ee7W+DwQgG02YnRWeKxSH/5yHViv3Nl8MIb4smH1wcyA8rP4AQ/Eq3xgkrry?= =?us-ascii?Q?cTWUOEZuajdcbO0UyVqasJsTiX5GhVuLL0y6S+bqgFpvEcWyBeP2WlZvHAFO?= =?us-ascii?Q?TKKGifx8P0ocmujCWttfQ0PK?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 240ef483-5ae9-4693-fa8e-08d97772e6b3 X-MS-Exchange-CrossTenant-AuthSource: VI1PR0401MB2559.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Sep 2021 11:29:23.2326 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: t3L/UWzNJmoudza3xm3y/L6BarVmW5COY04WYevXc4WOC2pbbj2FMOSHJoa93MAXGqANHH3kvpPixOm1QQ7QZQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0401MB2366 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 21-09-14 14:52:01, Jacky Bai wrote: > The PLLs used on i.MX8ULP is mostly the same as on i.MX7ULP, > except the PLL register offset is changed. Change the PLLv4 > driver for code reuse on i.MX7ULP and i.MX8ULP. > > Signed-off-by: Jacky Bai I'm OK with this one. But maybe later on we will have two separate wrappers in clk.h called imx_clk_hw_pllv4_7ulp and imx_clk_hw_pllv4_8ulp. We'll see. Reviewed-by: Abel Vesa > --- > v3 changes: no > --- > drivers/clk/imx/clk-imx7ulp.c | 4 ++-- > drivers/clk/imx/clk-pllv4.c | 34 +++++++++++++++++++++++++--------- > drivers/clk/imx/clk.h | 9 +++++++-- > 3 files changed, 34 insertions(+), 13 deletions(-) > > diff --git a/drivers/clk/imx/clk-imx7ulp.c b/drivers/clk/imx/clk-imx7ulp.c > index 779e09105da7..ba50d6db8097 100644 > --- a/drivers/clk/imx/clk-imx7ulp.c > +++ b/drivers/clk/imx/clk-imx7ulp.c > @@ -78,8 +78,8 @@ static void __init imx7ulp_clk_scg1_init(struct device_node *np) > hws[IMX7ULP_CLK_SPLL_PRE_DIV] = imx_clk_hw_divider_flags("spll_pre_div", "spll_pre_sel", base + 0x608, 8, 3, CLK_SET_RATE_GATE); > > /* name parent_name base */ > - hws[IMX7ULP_CLK_APLL] = imx_clk_hw_pllv4("apll", "apll_pre_div", base + 0x500); > - hws[IMX7ULP_CLK_SPLL] = imx_clk_hw_pllv4("spll", "spll_pre_div", base + 0x600); > + hws[IMX7ULP_CLK_APLL] = imx_clk_hw_pllv4(IMX_PLLV4_IMX7ULP, "apll", "apll_pre_div", base + 0x500); > + hws[IMX7ULP_CLK_SPLL] = imx_clk_hw_pllv4(IMX_PLLV4_IMX7ULP, "spll", "spll_pre_div", base + 0x600); > > /* APLL PFDs */ > hws[IMX7ULP_CLK_APLL_PFD0] = imx_clk_hw_pfdv2("apll_pfd0", "apll", base + 0x50c, 0); > diff --git a/drivers/clk/imx/clk-pllv4.c b/drivers/clk/imx/clk-pllv4.c > index 8ec703f27417..3c750ccbee25 100644 > --- a/drivers/clk/imx/clk-pllv4.c > +++ b/drivers/clk/imx/clk-pllv4.c > @@ -23,14 +23,17 @@ > > /* PLL Configuration Register (xPLLCFG) */ > #define PLL_CFG_OFFSET 0x08 > +#define IMX8ULP_PLL_CFG_OFFSET 0x10 > #define BP_PLL_MULT 16 > #define BM_PLL_MULT (0x7f << 16) > > /* PLL Numerator Register (xPLLNUM) */ > #define PLL_NUM_OFFSET 0x10 > +#define IMX8ULP_PLL_NUM_OFFSET 0x1c > > /* PLL Denominator Register (xPLLDENOM) */ > #define PLL_DENOM_OFFSET 0x14 > +#define IMX8ULP_PLL_DENOM_OFFSET 0x18 > > #define MAX_MFD 0x3fffffff > #define DEFAULT_MFD 1000000 > @@ -38,6 +41,9 @@ > struct clk_pllv4 { > struct clk_hw hw; > void __iomem *base; > + u32 cfg_offset; > + u32 num_offset; > + u32 denom_offset; > }; > > /* Valid PLL MULT Table */ > @@ -72,12 +78,12 @@ static unsigned long clk_pllv4_recalc_rate(struct clk_hw *hw, > u32 mult, mfn, mfd; > u64 temp64; > > - mult = readl_relaxed(pll->base + PLL_CFG_OFFSET); > + mult = readl_relaxed(pll->base + pll->cfg_offset); > mult &= BM_PLL_MULT; > mult >>= BP_PLL_MULT; > > - mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET); > - mfd = readl_relaxed(pll->base + PLL_DENOM_OFFSET); > + mfn = readl_relaxed(pll->base + pll->num_offset); > + mfd = readl_relaxed(pll->base + pll->denom_offset); > temp64 = parent_rate; > temp64 *= mfn; > do_div(temp64, mfd); > @@ -165,13 +171,13 @@ static int clk_pllv4_set_rate(struct clk_hw *hw, unsigned long rate, > do_div(temp64, parent_rate); > mfn = temp64; > > - val = readl_relaxed(pll->base + PLL_CFG_OFFSET); > + val = readl_relaxed(pll->base + pll->cfg_offset); > val &= ~BM_PLL_MULT; > val |= mult << BP_PLL_MULT; > - writel_relaxed(val, pll->base + PLL_CFG_OFFSET); > + writel_relaxed(val, pll->base + pll->cfg_offset); > > - writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET); > - writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET); > + writel_relaxed(mfn, pll->base + pll->num_offset); > + writel_relaxed(mfd, pll->base + pll->denom_offset); > > return 0; > } > @@ -207,8 +213,8 @@ static const struct clk_ops clk_pllv4_ops = { > .is_prepared = clk_pllv4_is_prepared, > }; > > -struct clk_hw *imx_clk_hw_pllv4(const char *name, const char *parent_name, > - void __iomem *base) > +struct clk_hw *imx_clk_hw_pllv4(enum imx_pllv4_type type, const char *name, > + const char *parent_name, void __iomem *base) > { > struct clk_pllv4 *pll; > struct clk_hw *hw; > @@ -221,6 +227,16 @@ struct clk_hw *imx_clk_hw_pllv4(const char *name, const char *parent_name, > > pll->base = base; > > + if (type == IMX_PLLV4_IMX8ULP) { > + pll->cfg_offset = IMX8ULP_PLL_CFG_OFFSET; > + pll->num_offset = IMX8ULP_PLL_NUM_OFFSET; > + pll->denom_offset = IMX8ULP_PLL_DENOM_OFFSET; > + } else { > + pll->cfg_offset = PLL_CFG_OFFSET; > + pll->num_offset = PLL_NUM_OFFSET; > + pll->denom_offset = PLL_DENOM_OFFSET; > + } > + > init.name = name; > init.ops = &clk_pllv4_ops; > init.parent_names = &parent_name; > diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h > index e144f983fd8c..3f518559b8f9 100644 > --- a/drivers/clk/imx/clk.h > +++ b/drivers/clk/imx/clk.h > @@ -42,6 +42,11 @@ enum imx_pll14xx_type { > PLL_1443X, > }; > > +enum imx_pllv4_type { > + IMX_PLLV4_IMX7ULP, > + IMX_PLLV4_IMX8ULP, > +}; > + > /* NOTE: Rate table should be kept sorted in descending order. */ > struct imx_pll14xx_rate_table { > unsigned int rate; > @@ -191,8 +196,8 @@ struct clk_hw *imx_clk_hw_pllv3(enum imx_pllv3_type type, const char *name, > .kdiv = (_k), \ > } > > -struct clk_hw *imx_clk_hw_pllv4(const char *name, const char *parent_name, > - void __iomem *base); > +struct clk_hw *imx_clk_hw_pllv4(enum imx_pllv4_type type, const char *name, > + const char *parent_name, void __iomem *base); > > struct clk_hw *clk_hw_register_gate2(struct device *dev, const char *name, > const char *parent_name, unsigned long flags, > -- > 2.26.2 >