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Tue, 14 Sep 2021 11:32:44 +0000 Date: Tue, 14 Sep 2021 14:32:42 +0300 From: Abel Vesa To: Jacky Bai Cc: shawnguo@kernel.org, robh+dt@kernel.org, sboyd@kernel.org, s.hauer@pengutronix.de, p.zabel@pengutronix.de, kernel@pengutronix.de, linux-imx@nxp.com, devicetree@vger.kernel.org Subject: Re: [PATCH v3 4/9] clk: imx: disable i.mx7ulp composite clock during initialization Message-ID: References: <20210914065208.3582128-1-ping.bai@nxp.com> <20210914065208.3582128-5-ping.bai@nxp.com> Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210914065208.3582128-5-ping.bai@nxp.com> X-ClientProxiedBy: VI1PR06CA0215.eurprd06.prod.outlook.com (2603:10a6:802:2c::36) To VI1PR0401MB2559.eurprd04.prod.outlook.com (2603:10a6:800:57::8) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from ryzen (188.25.164.198) by VI1PR06CA0215.eurprd06.prod.outlook.com (2603:10a6:802:2c::36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4500.14 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?cHsyGeUN5KUZuPLAMZxYsSrna+/HJyC6krH7Aq0xYdsEJ1KElaQtVu7KVvpZ?= =?us-ascii?Q?uOStDiXBBOKq8fz+OGz+HB+6TuU7OcSSRTdZqvc0JqkhWUTKJQmOxckGLNSf?= =?us-ascii?Q?jQznXsU/dnVKxYk8XPgk3MW+Dlx8g/6yDyGWyz6y7M4VIb9g/HqaERXN4mDI?= =?us-ascii?Q?VGkI1OUq02G0MuQpjy4mBs26IyNf3ADmIZykRJBkUn3QmwRmbbiC3MTjgot4?= =?us-ascii?Q?StLRQBinxiEHF+xsYowxfrO89gEJNjwG7vtnS/u1kBwuyoaL0nAlJDii1SEd?= =?us-ascii?Q?XnzZykwGG1Ovygrk16dCnCa2C+oTDIcPE/v5uCfDEOI60qmqKs1Wx5B7Fcsh?= =?us-ascii?Q?c9zReJaCl7tYy3HqB/EdybTphOqysB10D4mU5p3UB/LnimHN1xDcViQE03hf?= =?us-ascii?Q?y3aH7t+p1iWJkNGx2iN9dj3avBGQ0lw7gLBM8MHtI/82GBuLgHeiN2RFTmuL?= =?us-ascii?Q?sz3AfqeSQKokCgA3AtAcxwe2Wt1BE7cvMbXbJpjWQqNfA1FXOVoQEu8hMoMx?= =?us-ascii?Q?n6E4hL+uomFGiIXWZBnY4etAGFm64X9twp4kr0H40Xv9oSPJ88W6RW8M4lPL?= =?us-ascii?Q?MtO6ZorcScADZzaybb0I6y1jPAdOCS5+KCafreIpD2NXwvjAx00JDxb4eOCw?= =?us-ascii?Q?t8C/7K2P6iVXC3rGT+H+VkikNvElApUliR/x6svzPs2+i2v5/LuBKV/AKu2H?= =?us-ascii?Q?cGe+rA8pEb6l+VZmwDd7CRQ2LyVhqMb/SpPZRZ9TGgBG9R/r/mwc+dX4ofT7?= =?us-ascii?Q?lMNZ+vJA0k529l/qYD2OR/xHiRPQ5eKo0g8m1uXTr6uxBVXoD6emLgEQkgtw?= =?us-ascii?Q?hSs53Nmi/OAm+0pFceNGgwtTMJyp8g2RVVE9BYTfHr4sB+bhVwiwSsXd27Ji?= =?us-ascii?Q?CsmtfORxhYdeYiV63mFV0CUyp8gS3Wnyc48WpHMWklBOusBriAaaUhnTC2g1?= =?us-ascii?Q?MWBkZd/7aytnotpbKkNWx2bRDWHZRWVe9Ee089AaqstJh3OHS1DQxeO/jwnf?= =?us-ascii?Q?9f4d5ygVXqaqrUmz2HpsVKEG+mjD/oDYKwihx/n4ysqb1RGrC6blq+GbjbTb?= =?us-ascii?Q?x21ZW3WSzovnWUgCAhC77MEU6+gvPHFJcB8tKgDlGWCxpIYTIlOg1VH44T3q?= =?us-ascii?Q?Cej4hY0FWGfd45UnO9572UFecn2hrjAnMwytvQJ19dFarise0dSYY6rRIJ26?= =?us-ascii?Q?+B8Ap8tX1us3qJR0AUiuW1pbaKcsoWtbJ7sFhtGvP6JVat7D+5nhbaCUYOSN?= =?us-ascii?Q?ouYdTKm1VCZUFKBmsPuIixnTuD9OmkfDijndFqQa+cUGkf21m304iceni68n?= =?us-ascii?Q?JuigTddBa3nUg6UlnU4KD3Vj?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6385962e-9efd-41a2-21f0-08d977735ebc X-MS-Exchange-CrossTenant-AuthSource: VI1PR0401MB2559.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Sep 2021 11:32:44.6366 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: ZwyJxhCU81ystf7Z+37GZsBg26Ncv+hOHvwrdccRIWodEO/UbWoweGzj/pjM7FkUIY7gTOmxWj57QeSPSdMKtA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0401MB2638 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 21-09-14 14:52:03, Jacky Bai wrote: > From: Anson Huang > > i.MX7ULP peripheral clock ONLY allow parent/rate to be changed > with clock gated, however, during clock tree initialization, the > peripheral clock could be enabled by bootloader, but the prepare > count in clock tree is still zero, so clock core driver will allow > parent/rate changed even with CLK_SET_RATE_GATE/CLK_SET_PARENT_GATE > set, but the change will fail due to HW NOT allow parent/rate change > with clock enabled. It will cause clock HW status mismatch with > clock tree info and lead to function issue. Below is an example: > > usdhc0's pcc clock value is 0xC5000000 during kernel boot up, it > means usdhc0 clock is enabled, its parent is APLL_PFD1. In DT file, > the usdhc0 clock settings are as below: > > assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>; > assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>; > > when kernel boot up, the clock tree info is as below, but the usdhc0 > PCC register is still 0xC5000000, which means its parent is still > from APLL_PFD1, which is incorrect and cause usdhc0 NOT work. > > nic1_clk 2 2 0 176000000 0 0 50000 > usdhc0 0 0 0 176000000 0 0 50000 > > After making sure the peripheral clock is disabled during clock tree > initialization, the usdhc0 is working, and this change is necessary > for all i.MX7ULP peripheral clocks. > > Signed-off-by: Anson Huang Reviewed-by: Abel Vesa > --- > v3 changes: no > --- > drivers/clk/imx/clk-composite-7ulp.c | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/drivers/clk/imx/clk-composite-7ulp.c b/drivers/clk/imx/clk-composite-7ulp.c > index 50ed383320bf..92908ee4509d 100644 > --- a/drivers/clk/imx/clk-composite-7ulp.c > +++ b/drivers/clk/imx/clk-composite-7ulp.c > @@ -8,6 +8,7 @@ > #include > #include > #include > +#include > #include > > #include "../clk-fractional-divider.h" > @@ -73,6 +74,7 @@ static struct clk_hw *imx_ulp_clk_hw_composite(const char *name, > struct clk_gate *gate = NULL; > struct clk_mux *mux = NULL; > struct clk_hw *hw; > + u32 val; > > if (mux_present) { > mux = kzalloc(sizeof(*mux), GFP_KERNEL); > @@ -111,6 +113,18 @@ static struct clk_hw *imx_ulp_clk_hw_composite(const char *name, > gate_hw = &gate->hw; > gate->reg = reg; > gate->bit_idx = PCG_CGC_SHIFT; > + /* > + * make sure clock is gated during clock tree initialization, > + * the HW ONLY allow clock parent/rate changed with clock gated, > + * during clock tree initialization, clocks could be enabled > + * by bootloader, so the HW status will mismatch with clock tree > + * prepare count, then clock core driver will allow parent/rate > + * change since the prepare count is zero, but HW actually > + * prevent the parent/rate change due to the clock is enabled. > + */ > + val = readl_relaxed(reg); > + val &= ~(1 << PCG_CGC_SHIFT); > + writel_relaxed(val, reg); > } > > hw = clk_hw_register_composite(NULL, name, parent_names, num_parents, > -- > 2.26.2 >