From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4DCD3C433EF for ; Tue, 14 Sep 2021 15:59:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3546361155 for ; Tue, 14 Sep 2021 15:59:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235048AbhINQAz (ORCPT ); Tue, 14 Sep 2021 12:00:55 -0400 Received: from vps0.lunn.ch ([185.16.172.187]:40944 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235098AbhINQAz (ORCPT ); Tue, 14 Sep 2021 12:00:55 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=In-Reply-To:Content-Disposition:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:From:Sender:Reply-To:Subject: Date:Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding: Content-ID:Content-Description:Content-Disposition:In-Reply-To:References; bh=yP9sqpmeviA1gb8gdGm9Zr+sde7rymb2vu5e6GQu/qg=; b=DDxkZfiV6LZzhfKWyqCXV3BhOw QQgPt6wYz+nyhuYoBzaMdZICvs/MIrii8ETTiOfOOCa4wqAbXpitBrFSsmOgFusg/DHNyn8CqEhYg PXARVojjKYadX+59MKV9KVTZMnAcLKo43wQQXWIzbEHdYDF4BBEJ6FDrtr+TZ8tgN2O8=; Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1mQAqN-006cRo-UL; Tue, 14 Sep 2021 17:59:35 +0200 Date: Tue, 14 Sep 2021 17:59:35 +0200 From: Andrew Lunn To: Daniel Palmer Cc: devicetree@vger.kernel.org, robh+dt@kernel.org, maz@kernel.org, tglx@linutronix.de, linux-arm-kernel@lists.infradead.org, romain.perier@gmail.com Subject: Re: [PATCH 0/3] SigmaStar SSD20XD GPIO interrupt controller Message-ID: References: <20210914100415.1549208-1-daniel@0x0f.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210914100415.1549208-1-daniel@0x0f.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Tue, Sep 14, 2021 at 07:04:12PM +0900, Daniel Palmer wrote: > In new SigmaStar SoCs they have moved away from having a few > interrupt capable GPIOs and instead have chained yet another > interrupt controller in to provide interrupt support for > all of the GPIOs. > > I'm hardly an IRQ expert so I expect I've made a total > mess of this. No one else was going to write this driver > so I had a go. Hi Daniel How are the GPIOs mapped to the interrupts? Is it a simple 1:1? The GPIO core has some support for the GPIO drivers to be also interrupt controllers. So if this interrupt control is dedicated to GPIO, you would be better to make it part of the GPIO driver. Andrew