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From: Mark Brown <broonie@kernel.org>
To: Ricard Wanderlof <ricardw@axis.com>
Cc: Liam Girdwood <lgirdwood@gmail.com>,
	Rob Herring <robh+dt@kernel.org>,
	alsa-devel <alsa-devel@alsa-project.org>,
	devicetree@vger.kernel.org
Subject: Re: [PATCH 1/2] dt-bindings: sound: tlv320adc3xxx: New codec driver
Date: Mon, 4 Oct 2021 14:08:06 +0100	[thread overview]
Message-ID: <YVr8tqRoyyiWR4xl@sirena.org.uk> (raw)
In-Reply-To: <alpine.DEB.2.21.2110041115070.14472@lnxricardw1.se.axis.com>

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On Mon, Oct 04, 2021 at 11:17:47AM +0200, Ricard Wanderlof wrote:

> +  gpios:
> +    maxItems: 1
> +    description: GPIO pin used for codec reset (RESET pin)

Usually this would be called reset-gpios and/or have a name to improve
readability and allow for extensibility, from the binding we can see
that the device has other signals that can be used as GPIOs.

> +  ti,pll-mode:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    enum:
> +      - 0 # ADC3XXX_PLL_DONT_SET - leave mode unchanged
> +      - 1 # ADC3XXX_PLL_ENABLE - use the on-chip PLL
> +      - 2 # ADC3XXX_PLL_BYPASS - do not use the on-chip PLL
> +      - 3 # ADC3XXX_PLL_AUTO - use on-chip PLL if possible
> +    default: 0
> +    description: |
> +      Set on-chip PLL mode.
> +      ADC3XXX_PLL_DONT_SET is intended for use when setting the clock mod
> +      via the clock id in a machine driver and it is not to be changed
> +      from the previous setting.
> +      ADC3XXX_PLL_AUTO will enable  on-chip PLL if possible, depending on the
> +      master clock and sample rate combination.

Why is this configured through the DT binding and not via the machine
driver as done for other drivers?

> +      Note that there is currently no support for reading the GPIO pins as
> +      inputs.

This doesn't belong in the binding document, it's describing the binding
not any particular implementation.

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  reply	other threads:[~2021-10-04 13:19 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-04  9:17 [PATCH 1/2] dt-bindings: sound: tlv320adc3xxx: New codec driver Ricard Wanderlof
2021-10-04 13:08 ` Mark Brown [this message]
2021-10-04 15:16   ` Ricard Wanderlof
2021-10-04 15:20     ` Mark Brown

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