From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 929CAC433F5 for ; Fri, 22 Oct 2021 15:54:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6AE5560F6E for ; Fri, 22 Oct 2021 15:54:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233369AbhJVP4x (ORCPT ); Fri, 22 Oct 2021 11:56:53 -0400 Received: from mga14.intel.com ([192.55.52.115]:50470 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233328AbhJVP4w (ORCPT ); Fri, 22 Oct 2021 11:56:52 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10145"; a="229597260" X-IronPort-AV: E=Sophos;i="5.87,173,1631602800"; d="scan'208";a="229597260" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2021 08:54:34 -0700 X-IronPort-AV: E=Sophos;i="5.87,173,1631602800"; d="scan'208";a="534971271" Received: from smile.fi.intel.com ([10.237.72.184]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2021 08:54:28 -0700 Received: from andy by smile.fi.intel.com with local (Exim 4.95) (envelope-from ) id 1mdwrs-00099C-P1; Fri, 22 Oct 2021 18:54:04 +0300 Date: Fri, 22 Oct 2021 18:54:04 +0300 From: Andy Shevchenko To: Emil Renner Berthing Cc: linux-riscv , devicetree , linux-clk , "open list:GPIO SUBSYSTEM" , "open list:SERIAL DRIVERS" , Palmer Dabbelt , Paul Walmsley , Rob Herring , Michael Turquette , Stephen Boyd , Thomas Gleixner , Marc Zyngier , Philipp Zabel , Linus Walleij , Greg Kroah-Hartman , Daniel Lezcano , Jiri Slaby , Maximilian Luz , Sagar Kadam , Drew Fustini , Geert Uytterhoeven , Michael Zhu , Fu Wei , Anup Patel , Atish Patra , Matteo Croce , Linux Kernel Mailing List Subject: Re: [PATCH v2 09/16] reset: starfive-jh7100: Add StarFive JH7100 reset driver Message-ID: References: <20211021174223.43310-1-kernel@esmil.dk> <20211021174223.43310-10-kernel@esmil.dk> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Fri, Oct 22, 2021 at 05:36:21PM +0200, Emil Renner Berthing wrote: > On Fri, 22 Oct 2021 at 17:25, Andy Shevchenko wrote: > > On Fri, Oct 22, 2021 at 5:56 PM Emil Renner Berthing wrote: > > > On Fri, 22 Oct 2021 at 16:50, Andy Shevchenko wrote: > > > > On Fri, Oct 22, 2021 at 5:25 PM Emil Renner Berthing wrote: ... > > > > AFAICS they are sequential 4 32-bit registers. > > > > > > That's right, but we're on a 64bit machine, so DECLARE_BITMAP will > > > give us an unsigned long array that doesn't match that. > > > > I didn't get it, sorry. > > You will have a bitmap array which you will split to 32-bit values. > > What you will probably need is to move xgpio_get_value32() and void > > xgpio_set_value32() to the one of bitmap related headers (look for > > bitmap_get_value8() and friends). > > > > > > So bitmap is exactly what is suitable here, you are right! > > > > See gpio-xilinx and gpio-pca953x on how to use bitmaps in the GPIO drivers. > > > > > > None of them has a pre-initialized const DECLARE_BITMAP, so they don't > > > have to deal with the 4 vs. 2 commas problem. > > > > I believe it's well possible to refactor this to look much better with > > bitmaps (as it represents the hardware very well). > > Right, but how exactly? This works on on 64bit, but not with 32bit COMPILE_TEST: > > static const DECLARE_BITMAP(jh7100_reset_asserted, JH7100_RSTN_END) = { > /* STATUS0 register */ > BIT_MASK(JH7100_RST_U74) | > BIT_MASK(JH7100_RST_VP6_DRESET) | > BIT_MASK(JH7100_RST_VP6_BRESET) | > /* STATUS1 register */ > BIT_MASK(JH7100_RST_HIFI4_DRESET) | > BIT_MASK(JH7100_RST_HIFI4_BRESET), > /* STATUS2 register */ > BIT_MASK(JH7100_RST_E24) | > /* STATUS3 register */ > 0, > }; BITMAP_FROM_U64() ? > > > > > Also is there a macro for handling that we'd then need 4 commas on > > > > > 32bit COMPILE_TEST and 2 commas on 64bit? > > > > > If you have some other way in mind you'll have to be a lot more explicit again. > > > > > > > > > > The point of the jh7100_reset_asserted array is that it exactly > > > > > mirrors the values of the status registers when the lines are > > > > > asserted. -- With Best Regards, Andy Shevchenko