[v8 1/3] dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280

[v8 1/3] dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280

[Odelu Kukatla]

Add Epoch Subsystem (EPSS) L3 interconnect provider binding on SC7280
SoCs.

Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
---
 Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
index e701524..116e434 100644
--- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
+++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
@@ -18,6 +18,7 @@ properties:
   compatible:
     enum:
       - qcom,sc7180-osm-l3
+      - qcom,sc7280-epss-l3
       - qcom,sc8180x-osm-l3
       - qcom,sdm845-osm-l3
       - qcom,sm8150-osm-l3
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[v8 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider

[Odelu Kukatla]

Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280
SoCs.

Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index d74a4c8..0b55742 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -3687,6 +3687,14 @@
 			};
 		};
 
+		epss_l3: interconnect@18590000 {
+			compatible = "qcom,sc7280-epss-l3";
+			reg = <0 0x18590000 0 0x1000>;
+			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
+			clock-names = "xo", "alternate";
+			#interconnect-cells = <1>;
+		};
+
 		cpufreq_hw: cpufreq@18591000 {
 			compatible = "qcom,cpufreq-epss";
 			reg = <0 0x18591000 0 0x1000>,
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [v8 1/3] dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280

[Rob Herring]

On Thu, 21 Oct 2021 16:10:55 +0530, Odelu Kukatla wrote:
> Add Epoch Subsystem (EPSS) L3 interconnect provider binding on SC7280
> SoCs.
> 
> Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
> ---
>  Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

Re: [v8 1/3] dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280

[Stephen Boyd]

Quoting Odelu Kukatla (2021-10-21 03:40:55)
> Add Epoch Subsystem (EPSS) L3 interconnect provider binding on SC7280
> SoCs.
> 
> Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
> ---

Reviewed-by: Stephen Boyd <swboyd@chromium.org>

Re: [v8 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider

[Stephen Boyd]

Quoting Odelu Kukatla (2021-10-21 03:40:57)
> Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280
> SoCs.
> 
> Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
> ---

Reviewed-by: Stephen Boyd <swboyd@chromium.org>

Re: [v8 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider

[Bjorn Andersson]

On Thu 21 Oct 03:40 PDT 2021, Odelu Kukatla wrote:

> Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280
> SoCs.
> 
> Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
> ---
>  arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index d74a4c8..0b55742 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -3687,6 +3687,14 @@
>  			};
>  		};
>  
> +		epss_l3: interconnect@18590000 {
> +			compatible = "qcom,sc7280-epss-l3";
> +			reg = <0 0x18590000 0 0x1000>;

This series looks like I would expect, with and without per-core dcvs.
But can you please explain why this contradict what Sibi says here:
https://lore.kernel.org/all/1627581885-32165-3-git-send-email-sibis@codeaurora.org/

Regards,
Bjorn

> +			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
> +			clock-names = "xo", "alternate";
> +			#interconnect-cells = <1>;
> +		};
> +
>  		cpufreq_hw: cpufreq@18591000 {
>  			compatible = "qcom,cpufreq-epss";
>  			reg = <0 0x18591000 0 0x1000>,
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 

Re: [v8 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider

[okukatla]

On 2021-10-29 04:57, Bjorn Andersson wrote:
> On Thu 21 Oct 03:40 PDT 2021, Odelu Kukatla wrote:
> 
>> Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280
>> SoCs.
>> 
>> Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
>> ---
>>  arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 ++++++++
>>  1 file changed, 8 insertions(+)
>> 
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi 
>> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> index d74a4c8..0b55742 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> @@ -3687,6 +3687,14 @@
>>  			};
>>  		};
>> 
>> +		epss_l3: interconnect@18590000 {
>> +			compatible = "qcom,sc7280-epss-l3";
>> +			reg = <0 0x18590000 0 0x1000>;
> 
> This series looks like I would expect, with and without per-core dcvs.
> But can you please explain why this contradict what Sibi says here:
> https://lore.kernel.org/all/1627581885-32165-3-git-send-email-sibis@codeaurora.org/
> 
> Regards,
> Bjorn
> 
Thanks for Review!
Sibi's patch will be dropped, it is not required with my updated patch 
series:
https://lore.kernel.org/all/1627581885-32165-3-git-send-email-sibis@codeaurora.org/
>> +			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
>> +			clock-names = "xo", "alternate";
>> +			#interconnect-cells = <1>;
>> +		};
>> +
>>  		cpufreq_hw: cpufreq@18591000 {
>>  			compatible = "qcom,cpufreq-epss";
>>  			reg = <0 0x18591000 0 0x1000>,
>> --
>> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora 
>> Forum,
>> a Linux Foundation Collaborative Project
>> 

Re: [v8 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider

[Georgi Djakov]

On 21.10.21 13:40, Odelu Kukatla wrote:
> Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280
> SoCs.
> 
> Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>

Acked-by: Georgi Djakov <djakov@kernel.org>

> ---
>   arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 ++++++++
>   1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index d74a4c8..0b55742 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -3687,6 +3687,14 @@
>   			};
>   		};
>   
> +		epss_l3: interconnect@18590000 {
> +			compatible = "qcom,sc7280-epss-l3";
> +			reg = <0 0x18590000 0 0x1000>;
> +			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
> +			clock-names = "xo", "alternate";
> +			#interconnect-cells = <1>;
> +		};
> +
>   		cpufreq_hw: cpufreq@18591000 {
>   			compatible = "qcom,cpufreq-epss";
>   			reg = <0 0x18591000 0 0x1000>,
> 

Re: (subset) [v8 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider

[Bjorn Andersson]

On Thu, 21 Oct 2021 16:10:57 +0530, Odelu Kukatla wrote:
> Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280
> SoCs.
> 
> 

Applied, thanks!

[3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider
      commit: 8b93fbd95ed46bb0d57e63c65cef155a09a75bb9

Best regards,
-- 
Bjorn Andersson <bjorn.andersson@linaro.org>