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From: Jessica Clarke <jrtc27@jrtc27.com>
To: Atish Patra <atish.patra@wdc.com>
Cc: linux-kernel@vger.kernel.org, Anup Patel <anup.patel@wdc.com>,
	David Abdurachmanov <david.abdurachmanov@sifive.com>,
	devicetree@vger.kernel.org,
	Greentime Hu <greentime.hu@sifive.com>,
	Guo Ren <guoren@linux.alibaba.com>,
	Heinrich Schuchardt <xypron.glpk@gmx.de>,
	Jonathan Corbet <corbet@lwn.net>,
	linux-doc@vger.kernel.org, linux-perf-users@vger.kernel.org,
	linux-riscv@lists.infradead.org,
	Nick Kossifidis <mick@ics.forth.gr>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Rob Herring <robh+dt@kernel.org>,
	Vincent Chen <vincent.chen@sifive.com>
Subject: Re: [v4 10/11] riscv: dts: fu740: Add pmu node
Date: Thu, 28 Oct 2021 21:48:54 +0100	[thread overview]
Message-ID: <YXsMtrmuavGAHk8S@Jessicas-MacBook-Pro.local> (raw)
In-Reply-To: <20211025195350.242914-11-atish.patra@wdc.com>

On Mon, Oct 25, 2021 at 12:53:49PM -0700, Atish Patra wrote:
> HiFive unmatched supports HPMCounters but does not implement mcountinhibit
> or sscof extension. Thus, perf monitoring can be used on the unmatched
> board without sampling.
> 
> Add the PMU node with compatible string so that Linux perf driver can
> utilize this to enable PMU.
> 
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> ---
>  arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> index abbb960f90a0..b35b96b58820 100644
> --- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> @@ -140,6 +140,9 @@ soc {
>  		#size-cells = <2>;
>  		compatible = "simple-bus";
>  		ranges;
> +		pmu {
> +			compatible = "riscv,pmu";
> +		};

This is a property of the user-replaceable firmware, not a property of
the hardware, so having this in the device tree under /soc, let alone
hard-coded in Linux, is utterly wrong. Why can this not just be probed
like any other SBI interface? The "Probe SBI extension" interface is
precisely for this kind of thing.

Jess

  reply	other threads:[~2021-10-28 20:49 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-25 19:53 [v4 00/11] Improve RISC-V Perf support using SBI PMU and sscofpmf extension Atish Patra
2021-10-25 19:53 ` [v4 01/11] RISC-V: Remove the current perf implementation Atish Patra
2021-10-25 19:53 ` [v4 02/11] RISC-V: Add CSR encodings for all HPMCOUNTERS Atish Patra
2021-10-25 19:53 ` [v4 03/11] RISC-V: Add a perf core library for pmu drivers Atish Patra
2021-10-25 19:53 ` [v4 04/11] RISC-V: Add a simple platform driver for RISC-V legacy perf Atish Patra
2021-10-25 19:53 ` [v4 05/11] RISC-V: Add RISC-V SBI PMU extension definitions Atish Patra
2021-12-15  8:02   ` Nikita Shubin
2021-12-15 16:03     ` Atish Patra
2021-10-25 19:53 ` [v4 06/11] dt-binding: pmu: Add RISC-V PMU DT bindings Atish Patra
2021-10-26 18:03   ` Rob Herring
2021-10-26 18:57   ` Rob Herring
2021-10-28 20:17   ` Jessica Clarke
2021-10-25 19:53 ` [v4 07/11] RISC-V: Add perf platform driver based on SBI PMU extension Atish Patra
2021-10-25 19:53 ` [v4 08/11] RISC-V: Add interrupt support for perf Atish Patra
2021-10-25 19:53 ` [v4 09/11] Documentation: riscv: Remove the old documentation Atish Patra
2021-10-25 19:53 ` [v4 10/11] riscv: dts: fu740: Add pmu node Atish Patra
2021-10-28 20:48   ` Jessica Clarke [this message]
2021-10-28 23:37     ` Atish Patra
2021-10-29  0:07       ` Jessica Clarke
2021-10-29  6:05         ` Atish Patra
2021-10-29 12:25           ` Jessica Clarke
2021-10-25 19:53 ` [v4 11/11] MAINTAINERS: Add entry for RISC-V PMU drivers Atish Patra
2021-12-14  1:51 ` [v4 00/11] Improve RISC-V Perf support using SBI PMU and sscofpmf extension Palmer Dabbelt
2021-12-14  3:16   ` Atish Patra
2021-12-14 18:09   ` Will Deacon
2021-12-14  9:14 ` Nikita Shubin
2021-12-14 18:29   ` Atish Patra

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