Re: [RESEND PATCH 2/2] arm64: dts: sm8350: fix tlmm base address

[Bjorn Andersson <bjorn.andersson@linaro.org>]

On Tue 16 Nov 17:50 CST 2021, Katherine Perez wrote:

> TLMM controller base address is incorrect and will hang on some platforms.
> Fix by giving the correct address.
> 
> Signed-off-by: Katherine Perez <kaperez@linux.microsoft.com>
> ---
>  arch/arm64/boot/dts/qcom/sm8350.dtsi | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> index d134280e2939..624d294612d8 100644
> --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> @@ -960,9 +960,9 @@ spmi_bus: spmi@c440000 {
>  			#interrupt-cells = <4>;
>  		};
>  
> -		tlmm: pinctrl@f100000 {
> +		tlmm: pinctrl@f000000 {
>  			compatible = "qcom,sm8350-tlmm";
> -			reg = <0 0x0f100000 0 0x300000>;
> +			reg = <0 0x0f000000 0 0x300000>;

There's a group of register blocks related to TLMM starting at
0x0f000000 and then there's the register block that is relevant to the
OS that starts at 0x0f100000.

Downstream uses the group, while upstream describes only the hardware
block that's relevant to the OS. Unfortunately it seems that the shift
was missed for the UFS and SDC pins as the driver was upstreamed.

So I recently submitted this patch, which I expect would help you:
https://lore.kernel.org/all/20211104170835.1993686-1-bjorn.andersson@linaro.org/

Please let me know if that's not sufficient, or if I'm missed something
in my analysis.

Regards,
Bjorn

>  			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
>  			gpio-controller;
>  			#gpio-cells = <2>;
> -- 
> 2.31.1
>