From: Vinod Koul <vkoul@kernel.org>
To: Konrad Dybcio <konrad.dybcio@somainline.org>
Cc: Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
linux-arm-msm@vger.kernel.org,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Andy Gross <agross@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Vamsi Krishna Lanka <quic_vamslank@quicinc.com>,
linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 3/4] clk: qcom: Add clock driver for SM8450
Date: Tue, 7 Dec 2021 09:58:43 +0530 [thread overview]
Message-ID: <Ya7i+zfHhuiHFlYX@matsya> (raw)
In-Reply-To: <2649eada-3e80-cec3-5dca-bded67fa5f80@somainline.org>
On 01-12-21, 16:37, Konrad Dybcio wrote:
> On 01.12.2021 08:23, Vinod Koul wrote:
> > +static struct clk_alpha_pll gcc_gpll0 = {
> > + .offset = 0x0,
> > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
> > + .clkr = {
> > + .enable_reg = 0x62018,
> > + .enable_mask = BIT(0),
> > + .hw.init = &(struct clk_init_data){
> > + .name = "gcc_gpll0",
> > + .parent_data = &(const struct clk_parent_data){
> > + .fw_name = "bi_tcxo",
> > + .name = "bi_tcxo",
>
> I don't think we want .name for new drivers, as we do things cleanly
>
> from the start and don't have DT incompatibility problems.
Yes we need only fw_name here, I missed to remove this
> > +static int gcc_sm8450_probe(struct platform_device *pdev)
> > +{
> > + struct regmap *regmap;
> > + int ret;
> > +
> > + regmap = qcom_cc_map(pdev, &gcc_sm8450_desc);
> > + if (IS_ERR(regmap))
> > + return PTR_ERR(regmap);
> > +
> > + ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
> > + ARRAY_SIZE(gcc_dfs_clocks));
> > + if (ret)
> > + return ret;
> > +
> > + /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
> > + regmap_update_bits(regmap, gcc_ufs_phy_ice_core_clk.halt_reg, BIT(14), BIT(14));
> > +
> > + /* Keep the critical clock always-On
>
> I think the general style for multiline comments is to start with /* and then add a newline
Yes thanks for spotting, fixed
> > + * gcc_camera_ahb_clk, gcc_camera_xo_clk, gcc_disp_ahb_clk,
> > + * gcc_disp_xo_clk, gcc_gpu_cfg_ahb_clk, gcc_video_ahb_clk,
> > + * gcc_video_xo_clk
> > + */
> > + regmap_update_bits(regmap, 0x36004, BIT(0), BIT(0));
> > + regmap_update_bits(regmap, 0x36020, BIT(0), BIT(0));
> > + regmap_update_bits(regmap, 0x37004, BIT(0), BIT(0));
> > + regmap_update_bits(regmap, 0x3701c, BIT(0), BIT(0));
> > + regmap_update_bits(regmap, 0x81004, BIT(0), BIT(0));
> > + regmap_update_bits(regmap, 0x42004, BIT(0), BIT(0));
> > + regmap_update_bits(regmap, 0x42028, BIT(0), BIT(0));
> > +
> > + ret = qcom_cc_really_probe(pdev, &gcc_sm8450_desc, regmap);
> > + if (ret) {
> > + dev_err(&pdev->dev, "Failed to register GCC clocks\n");
>
> That's a bad downstream leftover that we don't want..
>
>
>
> > + return ret;
> > + }
> > +
> > + dev_info(&pdev->dev, "Registered GCC clocks\n");
>
> And so is this.
true will remove these
> > +
> > + return ret;
>
> You can simply return qcom_cc_really_probe(pdev, &gcc_sm8450_desc, regmap);
right!
--
~Vinod
next prev parent reply other threads:[~2021-12-07 4:28 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-01 7:23 [PATCH 0/4] clk: qcom: Add clocks for SM8450 SoC Vinod Koul
2021-12-01 7:23 ` [PATCH 1/4] dt-bindings: clock: Add SM8450 GCC clock bindings Vinod Koul
2021-12-01 7:23 ` [PATCH 2/4] dt-bindings: clock: Add RPMHCC bindings for SM8450 Vinod Koul
2021-12-01 7:23 ` [PATCH 3/4] clk: qcom: Add clock driver " Vinod Koul
2021-12-01 12:09 ` Dmitry Baryshkov
2021-12-01 15:37 ` Konrad Dybcio
2021-12-07 4:28 ` Vinod Koul [this message]
2021-12-01 19:40 ` kernel test robot
2021-12-07 9:32 ` Vinod Koul
2021-12-01 7:23 ` [PATCH 4/4] clk: qcom: rpmh: add support for SM8450 rpmh clocks Vinod Koul
2021-12-01 12:09 ` Dmitry Baryshkov
2021-12-01 15:38 ` Konrad Dybcio
2021-12-06 22:31 ` (subset) [PATCH 0/4] clk: qcom: Add clocks for SM8450 SoC Bjorn Andersson
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