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Date:   Wed, 1 Dec 2021 18:04:10 -0600
From:   Rob Herring <robh@kernel.org>
To:     Miquel Raynal <miquel.raynal@bootlin.com>
Cc:     Richard Weinberger <richard@nod.at>,
        Vignesh Raghavendra <vigneshr@ti.com>,
        Tudor Ambarus <Tudor.Ambarus@microchip.com>,
        Pratyush Yadav <p.yadav@ti.com>,
        Michael Walle <michael@walle.cc>,
        linux-mtd@lists.infradead.org, Mark Brown <broonie@kernel.org>,
        linux-spi@vger.kernel.org, devicetree@vger.kernel.org,
        Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
        Michal Simek <monstr@monstr.eu>
Subject: Re: [PATCH v2 4/5] spi: dt-bindings: Describe stacked/parallel
 memories modes
Message-ID: <YagNemH3SYHQJBTs@robh.at.kernel.org>
References: <20211126163450.394861-1-miquel.raynal@bootlin.com>
 <20211126163450.394861-5-miquel.raynal@bootlin.com>
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On Fri, Nov 26, 2021 at 05:34:49PM +0100, Miquel Raynal wrote:
> Describe two new memories modes:
> - A stacked mode when the bus is common but the address space extended
>   with an additinals wires.
> - A parallel mode with parallel busses accessing parallel flashes where
>   the data is spread.

I don't quite understand why this is in spi-controller.yaml.

Also, please see this series[1].

Rob

[1] https://lore.kernel.org/all/20211109181911.2251-1-p.yadav@ti.com/