From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0332CC433EF for ; Wed, 8 Dec 2021 18:16:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238746AbhLHSTf (ORCPT ); Wed, 8 Dec 2021 13:19:35 -0500 Received: from mail-ot1-f43.google.com ([209.85.210.43]:33593 "EHLO mail-ot1-f43.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238716AbhLHSTf (ORCPT ); Wed, 8 Dec 2021 13:19:35 -0500 Received: by mail-ot1-f43.google.com with SMTP id 35-20020a9d08a6000000b00579cd5e605eso3658140otf.0 for ; Wed, 08 Dec 2021 10:16:03 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=XJotKmVeKA5kF7Hhvq4nJ90VJRFbtJ+uslv7swmc13k=; b=XVLoX3SUlfv53WRkDhM3ZFXVK9KiNVPrukQ5eGeSAJpAI0ZxZJouLaQ4KFM+/Tr5IC gL7CY62aDHIRkQ3WQ8Mybtd3674LXeuEuXWnzeZwEpODBe9vClFRh8SzYBhXIpeXqElS sweumH6DfhAbMHHZHbxpfBQxtlflb/K320se4A1fi24vgdwh6dl/9d/k2LkxsVbZIg3o DsBb2btgCUTOlPERgJVUEYEme+tNA+ivrNHoLcJDDebT7+OsrOIKflTi8b1BgQ6OTPHU GmA160vULeBKZ+GPYkBtEGK2Bv4iqRcWa8V0d2GoWSODzjWFXxd93jwXzBSG4TCODz7Y wn+Q== X-Gm-Message-State: AOAM530p0klMkc96s4bfEDHDUDEdCOP+kL8tu04GGEkoHfa6GAHBBuZh ecgo7PPdsrQZQsZpQ2rthJoSv6Fa0A== X-Google-Smtp-Source: ABdhPJz30uYRA7CeRFR4nW7EzeqGZo3eYoOiFPEue43vOesGSO07EMMjCHBoV3bLHkSF2wYB1GJqtg== X-Received: by 2002:a9d:70ce:: with SMTP id w14mr1023485otj.77.1638987363122; Wed, 08 Dec 2021 10:16:03 -0800 (PST) Received: from robh.at.kernel.org (66-90-148-213.dyn.grandenetworks.net. [66.90.148.213]) by smtp.gmail.com with ESMTPSA id y192sm745006oie.21.2021.12.08.10.16.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Dec 2021 10:16:02 -0800 (PST) Received: (nullmailer pid 85688 invoked by uid 1000); Wed, 08 Dec 2021 18:16:01 -0000 Date: Wed, 8 Dec 2021 12:16:01 -0600 From: Rob Herring To: Robin Murphy Cc: will@kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com, suzuki.poulose@arm.com, thierry.reding@gmail.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Subject: Re: [PATCH 4/5] dt-bindings: perf: Convert Arm DSU to schema Message-ID: References: <9530f441a62c72c5a22a7b555ea42bbcd3b145a1.1638900542.git.robin.murphy@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <9530f441a62c72c5a22a7b555ea42bbcd3b145a1.1638900542.git.robin.murphy@arm.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Tue, Dec 07, 2021 at 06:20:42PM +0000, Robin Murphy wrote: > Convert the DSU binding to schema, as one does. > > Signed-off-by: Robin Murphy > --- > .../devicetree/bindings/arm/arm-dsu-pmu.txt | 27 ------------ > .../devicetree/bindings/perf/arm,dsu-pmu.yaml | 41 +++++++++++++++++++ > 2 files changed, 41 insertions(+), 27 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt > create mode 100644 Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml > > diff --git a/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt b/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt > deleted file mode 100644 > index 6efabba530f1..000000000000 > --- a/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt > +++ /dev/null > @@ -1,27 +0,0 @@ > -* ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU) > - > -ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores > -with a shared L3 memory system, control logic and external interfaces to > -form a multicore cluster. The PMU enables to gather various statistics on > -the operations of the DSU. The PMU provides independent 32bit counters that > -can count any of the supported events, along with a 64bit cycle counter. > -The PMU is accessed via CPU system registers and has no MMIO component. > - > -** DSU PMU required properties: > - > -- compatible : should be one of : > - > - "arm,dsu-pmu" > - > -- interrupts : Exactly 1 SPI must be listed. > - > -- cpus : List of phandles for the CPUs connected to this DSU instance. > - > - > -** Example: > - > -dsu-pmu-0 { > - compatible = "arm,dsu-pmu"; > - interrupts = ; > - cpus = <&cpu_0>, <&cpu_1>; > -}; > diff --git a/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml b/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml > new file mode 100644 > index 000000000000..b78b6b0fce66 > --- /dev/null > +++ b/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml > @@ -0,0 +1,41 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +# Copyright 2021 Arm Ltd. > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/perf/arm,dsu-pmu.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU) > + > +maintainers: > + - Suzuki K Poulose > + - Robin Murphy > + > +description: > + ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores with a shared > + L3 memory system, control logic and external interfaces to form a multicore > + cluster. The PMU enables gathering various statistics on the operation of the > + DSU. The PMU provides independent 32-bit counters that can count any of the > + supported events, along with a 64-bit cycle counter. The PMU is accessed via > + CPU system registers and has no MMIO component. > + > +properties: > + compatible: > + const: "arm,dsu-pmu" Don't need quotes. > + > + interrupts: > + items: > + description: nCLUSTERPMUIRQ interrupt - description: nCLUSTERPMUIRQ interrupt > + > + cpus: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + minitems: 1 > + maxitems: 8 > + description: List of phandles for the CPUs connected to this DSU instance. > + > +required: > + - compatible > + - interrupts > + - cpus > + > +additionalProperties: false > -- > 2.28.0.dirty > >