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From: Rob Herring <robh@kernel.org>
To: Dinh Nguyen <dinh.linux@gmail.com>
Cc: Pratyush Yadav <p.yadav@ti.com>,
	Dinh Nguyen <dinguyen@kernel.org>,
	devicetree@vger.kernel.org, broonie@kernel.org
Subject: Re: [PATCHv2 1/3] dt-bindings: spi: cadence-quadspi: document "cdns,qspi-nor-ver-00-10"
Date: Mon, 13 Dec 2021 14:48:48 -0600	[thread overview]
Message-ID: <YbexsGzz0/tuwjwq@robh.at.kernel.org> (raw)
In-Reply-To: <CADhT+wfrtqO6dDSUbq-eeyRodzigA7Gsce0xgK6mzLo0ujb5AQ@mail.gmail.com>

On Wed, Dec 08, 2021 at 05:45:31PM -0600, Dinh Nguyen wrote:
> On Mon, Dec 6, 2021 at 9:51 PM Pratyush Yadav <p.yadav@ti.com> wrote:
> >
> > On 03/12/21 12:17PM, Dinh Nguyen wrote:
> > > The QSPI controller on Intel's SoCFPGA platform does not implement the
> > > CQSPI_REG_WR_COMPLETION_CTRL register, thus a write to this register
> > > results in a crash.
> > >
> > > The module/revision ID is written in the MODULE_ID register. For this
> > > variance, bits 23-8 is 0x0010.
> >
> > When I looked at your original patches I was under the impression that
> > this was a SoCFPGA specific thing and did not apply to other
> > implementation of the IP in general.
> >
> > If this is indeed a generic thing and we can detect it via the MODULE_ID
> > register [0], then why not just read that register at probe time and
> > apply this quirk based on the ID? Why then do we need a separate
> > compatible at all?
> >
> > [0] I would like to see it stated explicitly somewhere that version
> > 0x0010 does not support the WR_COMPLETION_CTRL register.
> >
> 
> I cannot for sure confirm that this condition applies to only 0x0010
> version of the
> IP. I can verify that the IP that is in all 3 generations of SoCFPGA
> devices, all have
> MODULE_ID value of 0x0010 and all do not have the WR_COMPLETION_CTRL
> register implemented.

Then for the same reason, you shouldn't be trying to have a 'generic' 
compatible.

> 
> I'm almost certain this feature is not SoCFPGA specific, but
> since I only had SoCFPGA hardware, that was my initial patch. I made the mistake
> of not CC'ing the devicetree maintainers until I sent the DTS binding
> patch change,
> and he rightly suggested making the binding something more generic.

That is completely the opposite of what I said. You had something 
genericish to Intel platforms. You should make the compatible(s) SoC 
specific.


> I do like your idea of making a determination in the driver without
> being dependent
> on a dts binding. I'd like to know the impetus behind your original
> patch of removing the
> dependency of "if (f_pdata->dtr)"  for the write to the WR_COMPLETION_CTRL
> register? Perhaps there's some other common property that we can key
> off for why the register
> is not implemented?
> 
> Dinh
> 

  reply	other threads:[~2021-12-13 20:48 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-12-03 18:17 [PATCHv2 1/3] dt-bindings: spi: cadence-quadspi: document "cdns,qspi-nor-ver-00-10" Dinh Nguyen
2021-12-03 18:17 ` [PATCHv2 2/3] ARM: dts: socfpga: change qspi to "cdns,qspi-nor-ver-00-10" Dinh Nguyen
2021-12-03 18:17 ` [PATCH 3/3] spi: cadence-quadspi: change socfpga-qspi " Dinh Nguyen
2021-12-03 18:18 ` [PATCHv2 1/3] dt-bindings: spi: cadence-quadspi: document "cdns,qspi-nor-ver-00-10" Mark Brown
2021-12-03 19:05   ` Dinh Nguyen
2021-12-06 10:22 ` Pratyush Yadav
2021-12-08 23:45   ` Dinh Nguyen
2021-12-13 20:48     ` Rob Herring [this message]
2021-12-13 21:21       ` Dinh Nguyen
2021-12-14 20:05     ` Pratyush Yadav
2021-12-15 15:36       ` Dinh Nguyen
2021-12-16 18:58         ` Pratyush Yadav
  -- strict thread matches above, loose matches on Subject: below --
2021-12-03 17:32 Dinh Nguyen
2021-12-03 14:01 Dinh Nguyen

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