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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id p10sm181504otp.53.2021.12.14.19.41.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Dec 2021 19:41:18 -0800 (PST) Date: Tue, 14 Dec 2021 21:41:14 -0600 From: Bjorn Andersson To: Loic Poulain Cc: agross@kernel.org, robh+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, shawn.guo@linaro.org Subject: Re: [PATCH v2 2/2] dt-bindings: clock: Add qualcomm QCM2290 DISPCC bindings Message-ID: References: <1639058951-12660-1-git-send-email-loic.poulain@linaro.org> <1639058951-12660-2-git-send-email-loic.poulain@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1639058951-12660-2-git-send-email-loic.poulain@linaro.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Thu 09 Dec 08:09 CST 2021, Loic Poulain wrote: > Add device tree bindings for display clock controller on QCM2290 SoCs. > > Signed-off-by: Loic Poulain Reviewed-by: Bjorn Andersson Regards, Bjorn > --- > v2: no change > > .../bindings/clock/qcom,qcm2290-dispcc.yaml | 87 ++++++++++++++++++++++ > 1 file changed, 87 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/qcom,qcm2290-dispcc.yaml > > diff --git a/Documentation/devicetree/bindings/clock/qcom,qcm2290-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,qcm2290-dispcc.yaml > new file mode 100644 > index 00000000..44d5ce7 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/qcom,qcm2290-dispcc.yaml > @@ -0,0 +1,87 @@ > +# SPDX-License-Identifier: GPL-2.0-only > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/qcom,qcm2290-dispcc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm Display Clock & Reset Controller Binding for qcm2290 > + > +maintainers: > + - Loic Poulain > + > +description: | > + Qualcomm display clock control module which supports the clocks, resets and > + power domains on qcm2290. > + > + See also dt-bindings/clock/qcom,dispcc-qcm2290.h. > + > +properties: > + compatible: > + const: qcom,qcm2290-dispcc > + > + clocks: > + items: > + - description: Board XO source > + - description: Board active-only XO source > + - description: GPLL0 source from GCC > + - description: GPLL0 div source from GCC > + - description: Byte clock from DSI PHY > + - description: Pixel clock from DSI PHY > + > + clock-names: > + items: > + - const: bi_tcxo > + - const: bi_tcxo_ao > + - const: gcc_disp_gpll0_clk_src > + - const: gcc_disp_gpll0_div_clk_src > + - const: dsi0_phy_pll_out_byteclk > + - const: dsi0_phy_pll_out_dsiclk > + > + '#clock-cells': > + const: 1 > + > + '#reset-cells': > + const: 1 > + > + '#power-domain-cells': > + const: 1 > + > + reg: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - '#clock-cells' > + - '#reset-cells' > + - '#power-domain-cells' > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + #include > + clock-controller@5f00000 { > + compatible = "qcom,qcm2290-dispcc"; > + reg = <0x5f00000 0x20000>; > + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, > + <&rpmcc RPM_SMD_XO_A_CLK_SRC>, > + <&gcc GCC_DISP_GPLL0_CLK_SRC>, > + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, > + <&dsi0_phy 0>, > + <&dsi0_phy 1>; > + clock-names = "bi_tcxo", > + "bi_tcxo_ao", > + "gcc_disp_gpll0_clk_src", > + "gcc_disp_gpll0_div_clk_src", > + "dsi0_phy_pll_out_byteclk", > + "dsi0_phy_pll_out_dsiclk"; > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; > + }; > +... > -- > 2.7.4 >