From: Rob Herring <robh@kernel.org>
To: Marc Zyngier <maz@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, Mark Rutland <mark.rutland@arm.com>,
Will Deacon <will@kernel.org>, Hector Martin <marcan@marcan.st>,
Sven Peter <sven@svenpeter.dev>,
Alyssa Rosenzweig <alyssa@rosenzweig.io>,
Thomas Gleixner <tglx@linutronix.de>,
Dougall <dougallj@gmail.com>,
kernel-team@android.com
Subject: Re: [PATCH v3 03/10] dt-bindings: apple,aic: Add affinity description for per-cpu pseudo-interrupts
Date: Wed, 15 Dec 2021 15:35:16 -0600 [thread overview]
Message-ID: <YbpflHyduDzZb3vx@robh.at.kernel.org> (raw)
In-Reply-To: <20211214182634.727330-4-maz@kernel.org>
On Tue, Dec 14, 2021 at 06:26:27PM +0000, Marc Zyngier wrote:
> Some of the FIQ per-cpu pseudo-interrupts are better described with
> a specific affinity, the most obvious candidate being the CPU PMUs.
>
> Augment the AIC binding to be able to specify that affinity in the
> interrupt controller node.
>
> Signed-off-by: Marc Zyngier <maz@kernel.org>
> ---
> .../interrupt-controller/apple,aic.yaml | 26 +++++++++++++++++++
> 1 file changed, 26 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml
> index b95e41816953..ac1c82cffa0a 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml
> @@ -67,6 +67,32 @@ properties:
> Specifies base physical address and size of the AIC registers.
> maxItems: 1
>
> + affinities:
> + type: object
> + description:
> + FIQ affinity can be expressed as a single "affinities" node,
> + containing a set of sub-nodes, one per FIQ with a non-default
> + affinity.
> + patternProperties:
> + "^.+-affinity$":
> + type: object
> + properties:
> + fiq-index:
> + description:
> + The interrupt number specified as a FIQ, and for which
> + the affinity is not the default.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + maximum: 5
blank line between each prop.
> + affinity:
'cpus' is already somewhat established for list of phandles to cpu
nodes.
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + description:
> + Should be a list of phandles to CPU nodes (as described in
> + Documentation/devicetree/bindings/arm/cpus.yaml).
> +
> + required:
> + - fiq-index
> + - affinity
> +
> required:
> - compatible
> - '#interrupt-cells'
> --
> 2.30.2
>
>
next prev parent reply other threads:[~2021-12-15 21:35 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-14 18:26 [PATCH v3 00/10] drivers/perf: CPU PMU driver for Apple M1 Marc Zyngier
2021-12-14 18:26 ` [PATCH v3 01/10] dt-bindings: arm-pmu: Document Apple PMU compatible strings Marc Zyngier
2021-12-14 18:26 ` [PATCH v3 02/10] dt-bindings: apple,aic: Add CPU PMU per-cpu pseudo-interrupts Marc Zyngier
2021-12-14 18:26 ` [PATCH v3 03/10] dt-bindings: apple,aic: Add affinity description for " Marc Zyngier
2021-12-15 21:35 ` Rob Herring [this message]
2021-12-14 18:26 ` [PATCH v3 04/10] irqchip/apple-aic: Parse FIQ affinities from device-tree Marc Zyngier
2021-12-14 18:26 ` [PATCH v3 05/10] irqchip/apple-aic: Wire PMU interrupts Marc Zyngier
2021-12-14 18:26 ` [PATCH v3 06/10] arm64: dts: apple: Add t8103 PMU interrupt affinities Marc Zyngier
2021-12-14 18:26 ` [PATCH v3 07/10] arm64: dts: apple: Add t8301 PMU nodes Marc Zyngier
2021-12-14 18:48 ` Alyssa Rosenzweig
2021-12-14 18:26 ` [PATCH v3 08/10] irqchip/apple-aic: Move PMU-specific registers to their own include file Marc Zyngier
2021-12-14 18:26 ` [PATCH v3 09/10] drivers/perf: arm_pmu: Handle 47 bit counters Marc Zyngier
2021-12-14 18:26 ` [PATCH v3 10/10] drivers/perf: Add Apple icestorm/firestorm CPU PMU driver Marc Zyngier
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