From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8E0E4C433EF for ; Tue, 21 Dec 2021 14:33:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235543AbhLUOd6 (ORCPT ); Tue, 21 Dec 2021 09:33:58 -0500 Received: from mail-qt1-f173.google.com ([209.85.160.173]:42953 "EHLO mail-qt1-f173.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234548AbhLUOd5 (ORCPT ); Tue, 21 Dec 2021 09:33:57 -0500 Received: by mail-qt1-f173.google.com with SMTP id z9so12981387qtj.9 for ; Tue, 21 Dec 2021 06:33:57 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=aG0eQSYEAQyUQnUa/FOediZKLelTefKQEp1kjVjva0Q=; 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charset=us-ascii Content-Disposition: inline In-Reply-To: <20211220110630.3521121-12-s.hauer@pengutronix.de> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Mon, Dec 20, 2021 at 12:06:19PM +0100, Sascha Hauer wrote: > The VOP2 is found on newer Rockchip SoCs like the rk3568 or the rk3566. > The binding differs slightly from the existing VOP binding, so add a new > binding file for it. > > Signed-off-by: Sascha Hauer > --- > .../display/rockchip/rockchip-vop2.yaml | 146 ++++++++++++++++++ > 1 file changed, 146 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml > > diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml > new file mode 100644 > index 0000000000000..df14d5aa85c85 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml > @@ -0,0 +1,146 @@ > +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/rockchip/rockchip-vop2.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Rockchip SoC display controller (VOP2) > + > +description: > + VOP2 (Video Output Processor v2) is the display controller for the Rockchip > + series of SoCs which transfers the image data from a video memory > + buffer to an external LCD interface. > + > +maintainers: > + - Sandy Huang > + - Heiko Stuebner > + > +properties: > + compatible: > + enum: > + - rockchip,rk3566-vop > + - rockchip,rk3568-vop > + > + reg: > + minItems: 1 > + items: > + - description: > + Must contain one entry corresponding to the base address and length > + of the register space. > + - description: > + Can optionally contain a second entry corresponding to > + the CRTC gamma LUT address. > + > + interrupts: > + maxItems: 1 > + description: > + The VOP interrupt is shared by several interrupt sources, such as > + frame start (VSYNC), line flag and other status interrupts. > + > + clocks: > + items: > + - description: Clock for ddr buffer transfer. > + - description: Clock for the ahb bus to R/W the phy regs. > + - description: Pixel clock for video port 0. > + - description: Pixel clock for video port 1. > + - description: Pixel clock for video port 2. > + > + clock-names: > + items: > + - const: aclk_vop > + - const: hclk_vop _vop is redundant. > + - const: dclk_vp0 > + - const: dclk_vp1 > + - const: dclk_vp2 > + > + rockchip,grf: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: > + Phandle to GRF regs used for misc control > + > + ports: > + $ref: /schemas/graph.yaml#/properties/port s/port/ports/ > + > + properties: > + port@0: > + $ref: /schemas/graph.yaml#/properties/port > + description: > + Output endpoint of VP0 > + > + port@1: > + $ref: /schemas/graph.yaml#/properties/port > + description: > + Output endpoint of VP1 > + > + port@: port@2 > + $ref: /schemas/graph.yaml#/properties/port > + description: > + Output endpoint of VP2 > + > + assigned-clocks: true > + > + assigned-clock-rates: true > + > + assigned-clock-parents: true These are automatically added. > + > + iommus: > + maxItems: 1 > + > + power-domains: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - interrupts > + - clocks > + - clock-names > + - ports > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + #include > + bus { > + #address-cells = <2>; > + #size-cells = <2>; > + vop: vop@fe040000 { > + compatible = "rockchip,rk3568-vop"; > + reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>; > + interrupts = ; > + clocks = <&cru ACLK_VOP>, > + <&cru HCLK_VOP>, > + <&cru DCLK_VOP0>, > + <&cru DCLK_VOP1>, > + <&cru DCLK_VOP2>; > + clock-names = "aclk_vop", > + "hclk_vop", > + "dclk_vp0", > + "dclk_vp1", > + "dclk_vp2"; > + power-domains = <&power RK3568_PD_VO>; > + iommus = <&vop_mmu>; > + vop_out: ports { > + #address-cells = <1>; > + #size-cells = <0>; > + vp0: port@0 { > + reg = <0>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + vp1: port@1 { > + reg = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + vp2: port@2 { > + reg = <2>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + }; > + }; > + }; > -- > 2.30.2 > >