From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 39E7CC433F5 for ; Thu, 23 Dec 2021 11:33:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347950AbhLWLc7 (ORCPT ); Thu, 23 Dec 2021 06:32:59 -0500 Received: from dfw.source.kernel.org ([139.178.84.217]:51862 "EHLO dfw.source.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347908AbhLWLc7 (ORCPT ); Thu, 23 Dec 2021 06:32:59 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id C84E161E4D; Thu, 23 Dec 2021 11:32:58 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4B682C36AE5; Thu, 23 Dec 2021 11:32:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1640259178; bh=0RrhX3k1ZIV+bJYkPMaUSIE5xLzRFmh9h4IrE2Y0Ytc=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=U0N0zOxaG+hfvhbe6NMb7vBzhs0Y2RSCGxjDsFCD1+bUxqfzCTkUx1D5FGuLOEQTF PaTc0vmTs8slpuAwrPJwsuA+tx9JAe+vFYOn6sACHcMNakmwwfOPlGZJWaCrwim6y7 ZEVYQoy+09FlQmctw70t7E03e9UgsUqBY3YfFGtt2yXpmYgbIwMpRN+6L9HpQLHitF ryzZXuIokw3qZJ1qC7OHaIV5EKbGxVyMQTmdSpaIt6XgyQgQig1c/yvFpNBcuwM7G+ HwUF42Q2osVSofJq5Uk7v1uw/ZMGOvuvrxsX8qK1iyj3aAprsDveLmbQAJqO2TwAqE pfjMhO4k7joBg== Date: Thu, 23 Dec 2021 17:02:53 +0530 From: Vinod Koul To: Dmitry Baryshkov Cc: Andy Gross , Bjorn Andersson , Kishon Vijay Abraham I , Rob Herring , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH 0/2] phy: qcom-qmp: Add SM8450 PCIe1 PHY support Message-ID: References: <20211218141754.503661-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20211218141754.503661-1-dmitry.baryshkov@linaro.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 18-12-21, 17:17, Dmitry Baryshkov wrote: > There are two different PCIe PHYs on SM8450, one having one lane (v5) > and another with two lanes (v5.20). This series adds support for the > second PCIe phy. Applied, thanks -- ~Vinod